NXP Semiconductors PN544 C2 - RF Level Detector; RF Envelope TX; RF Signal RX

NXP Semiconductors
UM191812
PN544 C2 User Manual
191812 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
User Manual Rev. 1.2 — 2010-06-16 147 of 172
On GPIO5, the PN544 System Clock is output, 27.12 MHz.
To disable this setup:
-1- Perform a Hardware Reset (VEN pin use).
-2- Set GPIO7 and GPIO5 direction to their default configuration (depending of
application use).
9.19.3 RF Level Detector
To output RF Level Detector state to GPIO7, the following actions are needed:
-1- Set GPIO7 direction to Output.
-2- Set Debug_Interface to 0x44.
Then on GPIO7, the RF Level Detector is seen (1 = RF detected, 0 = No RF detected).
For further details on this signal, refer to [11] & [7].
To disa
ble this setup:
-1- Perform a Hardware Reset (VEN pin use).
-2- Set GPIO7 direction to its default configuration (depending of application use).
9.19.4 RF envelope TX
To output RF TX envelope to GPIO6, the following actions are needed:
-1- Set GPIO6 direction to Output.
-2- Set WI_SE_SigoutSel to 0x02 (TX envelope).
-3- Enable a Reader phase using HCI commands.
-4- Set Debug_Interface to 0x14.
For further details on this signal, refer to [11].
To disa
ble this setup:
-1- Perform a Hardware Reset (VEN pin use).
-2- Set WI_SE_SigoutSel to its default value (0x03).
-3- Set GPIO6 direction to its default configuration (depending of application use).
9.19.5 RF Signal RX
To output RF RX signals state to GPIO(s), the following actions are needed:
-1- Set GPIO(s) direction to Output.