NXP Semiconductors PN544 C2 - PN544 Configuration; SWP configuration

NXP Semiconductors
UM191812
PN544 C2 User Manual
191812 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
User Manual Rev. 1.2 — 2010-06-16 149 of 172
9.20 PN544 Configuration
PN544 can be customized thanks to the data EEPROM. The following settings can be
accessed using NXP_READ and NXP_WRITE commands (Refer to ‘PN544 System
Management’ chapter).
9.20.1 SWP configuration
Table 130. SWP configuration in EEPROM
Address Name Comment Default
0x9C01 SWP_Bitrate Indicates the bitrates to be used on SWP ‘according to UICC capability).
Supported bitrates are:
0x02 -> 212 kbit/s
0x04-> 424 kbit/s
0x08-> 848 kbit/s
0x10-> Maximum bitrate.
Others values are RFU
0x08
0x9C04 SWP_MiscConf - Bit0: Bit1: force the CRC to be OK for each frame received
- Bit3: if equal to 1 the RNR will be sent after ClearAllPipe command (and
other long processing command) instead of RR
- Bit4: if equal to 1 the soft reset in case of too many errors on RX is
activated
- Bit5: if equal to 1 the soft reset in case of too many errors on TX is
activated
- Others Bits are RFU
0x30
0x9EB4 SwpMgt_Request_Power Indicates if the power needs to be requested before a communication to the
UICC can be started in case the voltage on PMUVcc is already there but the
PMU is switched to low power mode.
- 0x00 -> no request
- 0x01 -> request through CLKREQ pin (GPIO pin 2 set to high when clock
requested, Hiz unless, whatever GPIO default configuration)
- 0x02 -> request through PWR_REQUEST pin (GPIO pin 3 set to high
when clock requested, Hiz unless, whatever GPIO default configuration)
- Others values are RFU
0x00
0x9C00 SWP_CurrentThreshold 0x02 -> 240 µA
0x12-> 260 µA
0x22-> 300 µA
0x32-> 330 µA
Others values are RFU
0x22