NXP Semiconductors PN544 C2 - PN544 Debug Mode; SWP Digitized; PLL Lock & System Clock

NXP Semiconductors
UM191812
PN544 C2 User Manual
191812 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
User Manual Rev. 1.2 — 2010-06-16 146 of 172
9.19 PN544 Debug Mode
This chapter describes the debug functionality of PN544 (i.e. Output signal on GPIO).
To setup the PN544 in debug mode, the following register has to be used:
Table 129. Debug_Interface Register
Address Name Comment Default
0xF830
Debug_Interface Debug_Interface Number
(default value 0x00 = No debug mode)
0x00
Using the Debug_Interface register, GPIO as output (See GPIO chapter) and setting
EEPROM Data area (See ‘0 cha
pter), the following debug mode can be used.
9.19.1 SWP digitized
To allow outputting SWP RX signal digitized to GPIO7, the following actions are needed:
-1- Set ANAIRQ_Conf - bit5 to 1 (i.e. 0x30).
-2- Reset PN544.
-3- Set GPIO7 direction to Output.
-4- Set Debug_Interface to 0x75.
Then on GPIO7, the SWP RX signal (S2 from UICC to PN544) digitized can be seen.
To disable this setup:
-1- Set ANAIRQ_Conf - bit5 to 0 (i.e. 0x10).
-2- Reset PN544.
-3- Set GPIO7 to its default configuration (depending of application use).
9.19.2 PLL Lock & System clock
PLL Lock and System clock signals can be output to GPIO7 and GPIO5.
To allow it, the following actions are needed:
-1- Set GPIO7 and GPIO5 direction to Output.
-2- Set Debug_Interface to 0x68.
Then on GPIO7, the PLL Lock state can be seen (1 = lock, 0 = unlock).