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NXP Semiconductors PN544 C2 - Page 2

NXP Semiconductors PN544 C2
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NXP Semiconductors
UM191812
PN544 C2 User Manual
191812 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
User Manual Rev. 1.2 — 2010-06-16 2 of 172
Contact information
For additional information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Revision history
Rev Date Description
1.0 2010-04-28 Release for PN544 C2
1.1 2010-05-07 Add register: TX_Current_Check, 0x9F14 change default value,
NXP_EVT_NFC_DEACTIVATED description update, Add NAD usage NfcT (0x98A3),
0x997A, 0x9F19 default value update, registers 0x998 and 0x9931 removed (trimmed
value – do not change), Fig 47 update
1.2 2010-06-16 Updates: 7.4.5 Error Detection and Error Handling, 49 Information Event, 9.8 MIFARE
PCD, 9.4.5 CLK request in NFC active target mode, 9.12.1 Initiator: added maximum frame
len
gth warning, typos, added list of tables and figures, Fig 7 HCI packet bigger than
maximum packet size, added EEPROM configurations SWP_Act_Retry, IFSLEW, Table
133 HW configuration in EEPROM, Table 13 HCI Gate Loopback, Type B PCD Anti-
collis
ion, Type B PICC HIGHER_LAYER_RESPONSE, RF Configuration in Polling Loop,
Host Link Timing restriction

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