Table 10. Capacitor recommendations to be placed near i.MX8 QXP
2
(continued)
Checkbox Supply
0.22
µF
1 µF
2.2
µF
10
µF
22 µF Notes
VDD_EMMC0_1P8_3P3 1 --- --- --- ---
VDD_EMMC0_VSELECT_1P8_3P3 1 --- --- --- ---
VDD_QSPI0A_1P8_3P3 2 --- --- --- ---
VDD_QSPI0B_1P8_3P3 2 --- --- --- ---
VDD_ENET0_VSELECT_1P8_2P5_3P
3
1
--- --- --- ---
VDD_ENET0_1P8_2P5_3P3 2 --- --- --- ---
VDD_ENET_MDIO_1P8_3P3 2 --- 1 --- ---
VDD_PCIE_1P8 2 --- 1 --- ---
Supply through a 120 Ω
ferrite bead.
VDD_PCIE_LDO_1P0_CAP 1 --- 1 --- ---
VDD_PCIE_DIG_1P8_3P3 2 --- --- --- ---
VDD_USB_SS3_LDO_1P0_CAP
VDD_USB_OTG_1P0
2 --- 1 --- ---
VDD_USB_1P8 2 --- 1 --- ---
Supply through one 120 Ω
ferrite bead.
VDD_USB_3P3 2 --- 1 --- ---
Note 1: All capacitors in MEK use the X7S or X7R grades.
Note 2: For PMIC capacitor recommendations, see the PMIC data sheet.
Table 11. PCIe recommendations
Checkbox Recommendation Explanation/Supplemental Recommendation
1. The reference clock source should have a HCSL
(High-Speed Current-Steering Logic) differential output.
Resistors of approximately 50 Ω are required to
terminate both traces to GND. Do not AC couple this
clock.
Note: i.MX6 processors used LVDS outputs for the PCIe
interface. The connection requirements are different for
this SOC.
The NXP development platform board design uses
a Micrel DSC557 device. However, NXP does not
recommend one supplier over another and it does
not suggest that this is the only clock generator
supplier. The particular device used should support
all specs (jitter, accuracy, and so on) The internal
PCIe reference clock is good for all standard PCIe
applications. The clock may be connected to one or
two external devices (depending on location). Use
a buffer, distributor, or external clock reference for
additional PCIe destinations.
Table continues on the next page...
NXP Semiconductors
i.MX8 QM and QXP design checklist
i.MX8 QM / i.MX8 QXP Hardware Developer’s Guide, Rev. 2.4p, 06/2021
User's Guide 15 / 89
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