Table 11. PCIe recommendations (continued)
Checkbox Recommendation Explanation/Supplemental Recommendation
The internal PCIe reference clock is not
spread spectrum capable. For EMC/EMI sensitive
applications, it is recommended to use an external
reference clock source.
2. The differential transmitters from the processor must
be AC coupled. Use a 0.22 µF cap on both the
PCIE_TXP and PCIE_TXN outputs.
PCIe specification compliance requires AC
coupling at each transmitter. The receiver must
be DC coupled.
3. The PCIE_REF_QR ball should be connected to
ground through a 453 Ω, 1 % resistor.
This signal is ball E23 on the i.MX8 QM and ball F12
on the i.MX8 QXP.
4. The PCIE_REXT ball should be connected to the
PCIE0_PHY_PLL_REF_RETURN ball through an 845 Ω,
0.5 % resistor.
PCIE_REXT is ball D22 (QM) and H12 (QXP).
PCIE_PHY_PLL_REF_RETURN is ball M28 (QM)
and ball G11 (QXP).
Note: The i.MX8 processor packages route
thePCIe RX and TX data pairs (including SATA) as
85- Ω differential impedance traces. NXP
recommends routing PCB differential traces to
match.
5. PCIE_SATA0_PHY_PLL_REF_RETURN,
PCIE0_PHY_PLL_REF_RETURN, and
PCIE1_PHY_PLL_REF_RETURN should be connected
to VDD_PCIE_1V8 by 0.22 µF capacitors (8QM).
See the i.MX8QM LPDDR4 MEK for the
correct implementation.
6. PCIE0_PHY_PLL_REF_RETURN should be
connected to VDD_PCIE_1V8 by 0.22 µF and 22 µF
capacitors (8QXP).
See the i.MX8QXP LPDDR4 MEK for the
correct implementation.
Table 12. USB recommendations
Checkbox Recommendation Explanation/Supplemental Recommendation
1. To comply with the USB OTG specification, the
VBUS supply to the OTG connector should default
to off when the board powers up.
The processor should turn on VBUS if required.
2. Connect a 499 Ω, 1 % resistor to ground on the
USB_OTG2_REXT ball (ball E29 on QM and ball
D14 on QXP.
3. Connect a 499 Ω, 1 % resistor to ground on the
USB_SS3_REXT ball (ball E27 on QM, ball E13 on
QXP).
4. If using USB1 OTG, connect USB_OTG1_VBUS
(ball A39 on QM and ball H18 on QXP) to the 5 V
OTG connector VBUS.
If unused, leave VBUS unconnected.
Table continues on the next page...
NXP Semiconductors
i.MX8 QM and QXP design checklist
i.MX8 QM / i.MX8 QXP Hardware Developer’s Guide, Rev. 2.4p, 06/2021
User's Guide 16 / 89
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