NXP Semiconductors i.MX8 QM - Page 42

impedance (the exception is that if the trace length is less than 30 mils, a 52 Ω impedance may be used). The remaining
trace segments should use a 52 Ω single-ended trace impedance
2
.
• Place the series resistors on the top layer to reduce the number of vias used. The series resistors on the differential pair
CLK can be placed on the bottom layer. The via number can be increased. As a rule of thumb, the number of vias used
should be equal to (or less than) the number of IC devices. Example: If there are four devices including the CPU, the max
via number should be 4.
• The termination resistor should be 40 Ω and it should be connected to the VTT supply. Capacitor placement on the VTT is
very important and NXP recommends at least one decoupling capacitor for every three traces connected to the VTT.
• Consider the trace that connects the processor ball to the termination resistor at the end of the trace as the main portion
of the trace. The trace portions that branch off this main trace (typically through a via) going to each of the three DDRL
devices are considered stubs. The three stub lengths should be matched in length, and their length should be between
170 mil and 360 mil, based on NXP simulations.
• The NXP validation board layout is available for further reference.
• If ECC is not used and there are only two 16-bit DDR devices in the design, the validation board layout strategy for the
command/address traces can still be used. Simply remove the first (closest to the processor) device and trace stub.
• Regardless of whether the NXP layout is used as a base or a new layout is created from scratch, running signal analysis
using simulation tools (Sigrity, Hyperlynx) is highly recommended.
NOTE 1,2: if 40 Ω and 52 Ω impedance controls are hard to achieve, make them as near as possible to the target value.
The following figures show the placement and routing of the DDR3L signals on the i.MX8 QXP DDR3L validation board.
NXP Semiconductors
i.MX8 layout/routing recommendations
i.MX8 QM / i.MX8 QXP Hardware Developer’s Guide, Rev. 2.4p, 06/2021
User's Guide 42 / 89