Table 16. DDR3L/LPDDR4 connectivity (continued)
Ball Name QXP Ball # QM Ball #
DDR3L
function (QXP)
LPDDR4 function
(QM, QXP)
DDR_DCF01 U3 W47 W7 A6 CA4_A
DDR_DCF02 ----- Y48 Y6 ----- -----
DDR_DCF03 U1 Y46 Y8 A7 CA5_A
DDR_DCF04 U7 W43 W11 A8 -----
DDR_DCF05 U5 Y44 Y10 A9 -----
DDR_DCF06 ----- W45 W9 ----- -----
DDR_DCF07 T2 W51 W3 RAS# -----
DDR_DCF08 AB4 T48 T6 A3 CA3_A
DDR_DCF09 AB6 T52 T2 ODT0 -----
DDR_DCF10 AC5 T50 T4 A1 CS0_A
DDR_DCF11 W3 U51 U3 A0 CA0_A
DDR_DCF12 Y8 U49 U5 A2 CS1_A
DDR_DCF13 ----- T46 T8 ----- -----
DDR_DCF14 Y2 W53 W1 ----- CKE0_A
DDR_DCF15 Y4 Y52 Y2 ----- CKE1_A
DDR_DCF16 W7 U53 U1 A4 CA1_A
DDR_DCF17 N3 AC47 AC7 A12 CA4_B
DDR_DCF18 L1 AB48 AB6 RESET_N RESET_N
DDR_DCF19 N1 AB46 AB8 A14 CA5_B
DDR_DCF20 P4 AC43 AC11 A15 -----
DDR_DCF21 T8 AE45 AE9 BA0 -----
DDR_DCF22 P2 AC51 AC3 BA1 -----
DDR_DCF23 T4 AC45 AC9 BA2 -----
DDR_DCF24 T6 AB44 AB10 CAS# -----
DDR_DCF25 K8 AF52 AF2 ODT1 -----
Table continues on the next page...
NXP Semiconductors
i.MX8 layout/routing recommendations
i.MX8 QM / i.MX8 QXP Hardware Developer’s Guide, Rev. 2.4p, 06/2021
User's Guide 22 / 89
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