NXP Semiconductors i.MX8 QM - Page 34

Table 22. i.MX8 QM LPDDR4-3200 routing recommendations
LPDDR4-3200
LPDDR4 signal
(each 16-
bit channel)
Group
PCB and Package Prop Delay
Considerations
Min Max
CK_t/CK_c Clock
As short
as possible
225 ps (do not exceed
1125 mils)
Match the true/complement signals
within 1 ps (the timing includes the
package length).
Incorporate package lengths/delays
into the constraint manager.
CA[5:0]
Address/
Command/
Control
CK_t + package
length -1 ps
CK_t + package
length + 1 ps
Keep the maximum total PCB +
package length skew of CA/CTL bus
within + 1.0 ps of CK_t.
Incorporate package lengths/delays
into the constraint manager.
CS
CKE
DQ[7:0]
Byte 0
As short
as possible
190 ps (260 ps with
package delta) do not
exceed 1150 mils)
Match the differential signals of DQS
within 1.0 ps. Keep the maximum total
PCB + package delta skew of each
DQS/DQ/DMI slice within + 1.0 ps.
Incorporate package lengths/delays
into the constraint manager.
DM0
DQS0_t/DQS0_c
DQ[15:8]
Byte1
As short
as possible
190 ps (260 ps with
package delta) do not
exceed 1150 mils)
DM1
DQS1_t/DQS1_c
The following figures show the placement and routing of the LPDDR4 signals on the i.MX8 QM development (MEK) platform.
Note from the schematic that the individual bits and byte lanes are swapped between the processor and the LPDDR4 memories.
It should also be noted that the swapping is different between the west side and east side memories (left and right sides of the
processor, respectively). This was done to ease routing and this connectivity scheme should be duplicated on a customer design
using LPDDR4.
The back side of the PCB (layer 12) is used for signal routing, but it had no LPDDR4 signals on it, and is thus not shown.
NXP Semiconductors
i.MX8 layout/routing recommendations
i.MX8 QM / i.MX8 QXP Hardware Developer’s Guide, Rev. 2.4p, 06/2021
User's Guide 34 / 89