NXP Semiconductors i.MX8 QM - Page 37

Table 23. i.MX8 QXP LPDDR4-2400 routing recommendations
LPDDR4-2400
LPDDR4 signal
(each 16-
bit channel)
Group
PCB and Package Prop Delay
Considerations
Min Max
CK_t/CK_c Clock
As short
as possible
225 ps
Match the true/complement signals
within 1.5 ps (PCB + package).
Incorporate package lengths/delays
into the constraint manager.
CA[5:0]
Address/
Command/
Control
CK_t + package
length -1.5 ps
CK_t + package
length + 1.5 ps
Keep the maximum delay skew of the
CA/CTL bus within + 1.5 ps of CK_t.
Incorporate package lengths/delays
into the constraint manager.
CS
CKE
DQ[7:0]
Byte 0
As short
as possible
300 ps
Keep the maximum total PCB
+ package length skew of each
DQS/DQ/DMI slice within
+ 1.5 ps.
Incorporate package lengths/delays
into the constraint manager.
DM0
DQS0_t/DQS0_c
DQ[15:8]
Byte1
As short
as possible
300 ps
DM1
DQS1_t/DQS1_c
The following figures show the placement and routing of the LPDDR4 signals on the i.MX8 QXP MEK development platform. Note
from the schematic that the individual bits and byte lanes are swapped between the processor and the LPDDR4 memories. This
was done to ease routing and this connectivity scheme should be duplicated on customer designs using LPDDR4.
The back side of the PCB (layer 8) is used for signal routing, but it had no LPDDR4 signals on it, and is thus not shown.
NXP Semiconductors
i.MX8 layout/routing recommendations
i.MX8 QM / i.MX8 QXP Hardware Developer’s Guide, Rev. 2.4p, 06/2021
User's Guide 37 / 89