NXP Semiconductors i.MX8 QM - Page 5

Table 1. Definitions and acronyms
Acronym Definition
ARM Advanced RISC Machines processor architecture
BGA Ball Grid Array package
BOM Bill Of Materials
BSDL Boundary Scan Description Language
CAN Flexible Controller Area Network peripheral
CCM Clock Controller Module
CSI MIPI Camera Serial Interface
DDR Dual Data Rate DRAM
DDR3L Low-voltage DDR3 DRAM
DDRC DDR Controller
DFP Downstream Facing Port (USB Type-C)
DRP Dual Role Port (USB Type-C)
ECSPI Enhanced Configurable SPI peripheral
EIM External Interface Module
ENET 10/100/1000 Mbps Ethernet MAC peripheral
EPIT Enhanced Periodic Interrupt Timer peripheral
ESR Equivalent Series Resistance
GND Ground
GPC General Power Controller
GPIO General-Purpose Input/Output
HDCP High-bandwidth Digital Content Protection
I
2
C Inter-integrated Circuit interface
IBIS Input output Buffer Information Specification
IOMUX i.MX8 chip-level I/O Multiplexing
JTAG Joint Test Action Group
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NXP Semiconductors
Overview
i.MX8 QM / i.MX8 QXP Hardware Developer’s Guide, Rev. 2.4p, 06/2021
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