LPC5411x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved.
Product data sheet Rev. 2.1 — 9 May 2018 6 of 105
NXP Semiconductors
LPC5411x
32-bit ARM Cortex-M4/M0+ microcontroller
The LPC5411x LQFP64 package has the following top-side marking:
• First line: LPC5411xJyyy
– x: 4 = dual core (M4, M0+)
– x: 3 = single core (M4)
– yyy: flash size
• Second line: BD64
• Third line: xxxxxxxxxxxx
• Fourth line: xxxyywwx[R]x
– yyww: Date code with yy = year and ww = week.
– xR = Boot code version and device revision.
The LPC5411x WLCSP49 package has the following top-side marking:
• First line: LPC5411x
– x: 4 = dual core (M4, M0+)
– x: 3 = single core (M4)
• Second line: JxxxUK49
– xxx: flash size
• Third line: xxxxxxxx
• Fourth line: xxxyyww
– yyww: Date code with yy = year and ww = week.
• Fifth line: xxxxx
• Sixth line: NXP x[R]x
– xR = Boot code version and device revision.
Table 3. Device revision table
Revision description
‘0A’ Initial device revision with boot code version 18.0.
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