LPC5411x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved.
Product data sheet Rev. 2.1 — 9 May 2018 23 of 105
NXP Semiconductors
LPC5411x
32-bit ARM Cortex-M4/M0+ microcontroller
The MPU allows separating processing tasks by disallowing access to each other's data,
disabling access to memory regions, allowing memory regions to be defined as read-only
and detecting unexpected memory accesses that could potentially break the system.
The MPU separates the memory into distinct regions and implements protection by
preventing disallowed accesses. The MPU supports up to eight regions each of which can
be divided into eight subregions. Accesses to memory locations that are not defined in the
MPU regions, or not permitted by the region setting, will cause the Memory Management
Fault exception to take place.
7.6 Nested Vectored Interrupt Controller (NVIC) for Cortex-M4
The NVIC is an integral part of the Cortex-M4. The tight coupling to the CPU allows for low
interrupt latency and efficient processing of late arriving interrupts.
7.6.1 Features
• Controls system exceptions and peripheral interrupts.
• 40 vectored interrupt slots.
• Eight programmable interrupt priority levels, with hardware priority level masking.
• Relocatable vector table using Vector Table Offset Register (VTOR).
• Non-Maskable Interrupt (NMI).
• Software interrupt generation.
7.6.2 Interrupt sources
Each peripheral device has one interrupt line connected to the NVIC but may have several
interrupt flags.
7.7 Nested Vectored Interrupt Controller (NVIC) for Cortex-M0+
The NVIC is an integral part of the Cortex-M0+. The tight coupling to the CPU allows for
low interrupt latency and efficient processing of late arriving interrupts.
7.7.1 Features
• Controls system exceptions and peripheral interrupts.
• 32 vectored interrupt slots.
• Four programmable interrupt priority levels, with hardware priority level masking.
• Relocatable vector table using VTOR.
• Non-Maskable Interrupt (NMI).
• Software interrupt generation.
7.7.2 Interrupt sources
Each peripheral device has one interrupt line connected to the NVIC but may have several
interrupt flags.
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