LPC5411x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved.
Product data sheet Rev. 2.1 — 9 May 2018 38 of 105
NXP Semiconductors
LPC5411x
32-bit ARM Cortex-M4/M0+ microcontroller
• Activity on the USART synchronous slave mode allows wake-up from deep-sleep
mode on any enabled interrupt
7.19.5 SPI serial I/O controller
7.19.5.1 Features
• Master and slave operation.
• Maximum data rate of 48 Mbit/s in master mode and 15 Mbit/s in slave mode for SPI
functions.
• Data frames of 1 to 16 bits supported directly. Larger frames supported by software or
DMA set-up.
• Master and slave operation.
• Data can be transmitted to a slave without the need to read incoming data. This can
be useful while setting up an SPI memory.
• Control information can optionally be written along with data. This allows very
versatile operation, including “any length” frames.
• Four Slave Select input/outputs with selectable polarity and flexible usage.
• Activity on the SPI in slave mode allows wake-up from deep-sleep mode on any
enabled interrupt.
Remark: Texas Instruments SSI and National Microwire modes are not supported.
7.19.6 I
2
C-bus interface
The I
2
C-bus is bidirectional for inter-IC control using only two wires: a serial clock line
(SCL) and a serial data line (SDA). Each device is recognized by a unique address and
can operate as either a receiver-only device (for example, an LCD driver) or a transmitter
with the capability to both receive and send information (such as memory). Transmitters
and/or receivers can operate in either master or slave mode, depending on whether the
chip has to initiate a data transfer or is only addressed. The I
2
C is a multi-master bus and
can be controlled by more than one bus master connected to it.
7.19.7 Features
• Independent Master, Slave, and Monitor functions.
• Bus speeds supported:
– Standard mode, up to 100 kbits/s.
– Fast-mode, up to 400 kbits/s.
– Fast-mode Plus, up to 1 Mbits/s (on specific I
2
C pins).
– High speed mode, 3.4 Mbits/s as a Slave only (on specific I
2
C pins).
• Supports both Multi-master and Multi-master with Slave functions.
• Multiple I2C slave addresses supported in hardware.
• One slave address can be selectively qualified with a bit mask or an address range in
order to respond to multiple I
2
C bus addresses.
• 10-bit addressing supported with software assist.
• Supports System Management Bus (SMBus).
• Separate DMA requests for Master, Slave, and Monitor functions.
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