LPC5411x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved.
Product data sheet Rev. 2.1 — 9 May 2018 30 of 105
NXP Semiconductors
LPC5411x
32-bit ARM Cortex-M4/M0+ microcontroller
Table 9 describes signals on the clocking diagram.
7.13.3 Brownout detection
The LPC5411x includes a monitor for the voltage level on the V
DD
pin. If this voltage falls
below a fixed level, the BOD sets a flag that can be polled or cause an interrupt. In
addition, a separate threshold levels can be selected to cause chip reset and interrupt.
7.13.4 Safety
The LPC5411x includes a Windowed WatchDog Timer (WWDT), which can be enabled by
software after reset. Once enabled, the WWDT remains locked and cannot be modified in
any way until a reset occurs.
7.14 Code security (Code Read Protection - CRP)
This feature of the LPC5411x allows user to enable different levels of security in the
system so that access to the on-chip flash and use of the Serial Wire Debugger (SWD)
and In-System Programming (ISP) can be restricted. When needed, CRP is invoked by
programming a specific pattern into a dedicated flash location. IAP commands are not
affected by the CRP.
In addition, ISP entry can be invoked by pulling a pin on the LPC5411x LOW on reset.
This pin is called the ISP entry pin.
There are three levels of Code Read Protection:
1. CRP1 disables access to the chip via the SWD and allows partial flash update
(excluding flash sector 0) using a limited set of the ISP commands. This mode is
useful when CRP is required and flash field updates are needed but all sectors cannot
be erased.
2. CRP2 disables access to the chip via the SWD and only allows full flash erase and
update using a reduced set of the ISP commands.
3. CRP3 fully disables any access to the chip via SWD and ISP. It is up to the user’s
application to provide (if needed) flash update mechanism using IAP calls or a call to
reinvoke ISP command to enable a flash update via USART.
Table 7. Clocking diagram signal name descriptions
Name Description
32k_clk The 32 kHz output of the RTC oscillator. The 32 kHz clock must be enabled in the RTCOSCCTRL register.
clk_in This is the internal clock that comes from the main CLK_IN pin function. That function must be connected to the
pin by selecting it in the IOCON block.
frg_clk The output of the Fractional Rate Generator.
fro_12m The 12 MHz output of the currently selected on-chip FRO oscillator.
fro_hf The currently selected FRO high speed output. This may be either 96 MHz or 48 MHz.
main_clk The main clock used by the CPU and AHB bus, and potentially many others.
mclk_in The MCLK input function, when it is connected to a pin by selecting it in the IOCON block.
pll_clk The output of the PLL.
wdt_clk The output of the watchdog oscillator, which has a selectable target frequency. It must also be enabled in the
PDRINCFG0 register.
“none” A tied-off source that should be selected to save power when the output of the related multiplexer is not used.
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