LPC5411x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved.
Product data sheet Rev. 2.1 — 9 May 2018 29 of 105
NXP Semiconductors
LPC5411x
32-bit ARM Cortex-M4/M0+ microcontroller
Fig 8. LPC5411x clock generation
000
001
010
pll_clk
main_clk
main_clk
fro_hf
111
“none”
ADC CLOCK
DIVIDER
to ADC
ADCCLKDIV
CPU CLOCK
DIVIDER
system clock to
CPU, AHB bus,
Sync APB, etc.
AHBCLKDIV
ADC clock select
ADCCLKSEL[2:0]
SYSTEM PLL
(PLL0)
System PLL
settings
to async
APB bridge
000
001
010
pll_clk
fro_hf
main_clk
111
“none”
USB CLOCK
DIVIDER
to FS USB
USBCLKDIV
USB clock select
USBCLKSEL[2:0]
00
01
10
clk_in
fro_12m
(1)
(1)
wdt_clk
11
fro_hf
00
10
11
pll_clk
32k_clk
Main clock select A
MAINCLKSELA[1:0]
00
01
fro_12m
main_clk
(1)
(1): synchronized multiplexer,
see register descriptions for details.
APB clock select B
ASYNCAPBCLKSELB[1:0]
Main clock select B
MAINCLKSELB[1:0]
000
001
010
clk_in
fro_12m
wdt_clk
011
32k_clk
111
“none”
PLL clock select
SYSPLLCLKSEL[2:0]
FRG CLOCK
DIVIDER
FRGCTRL[15:0]
000
001
010
pll_clk
main_clk
fro_12m
011
fro_hf
111
“none”
FRG clock select
FRGCLKSEL[2:0]
000
001
010
fro_hf
fro_12
pll_clk
011
mclk_in
100
frg_clk
111
“none”
aaa-022102
Function clock select
FXCOMCLKSEL[n][2:0]
fcn_fclk
(function clock
of Flexcomm [n]
CLKOUT
DIVIDER
CLKOUT
CLKOUTDIV
000
001
010
clk_in
main_clk
wdt_clk
011
fro_hf
100
pll_clk
101
fro_12m
110
32k_clk
111
“none”
CLKOUT select
CLKOUTSELA[2:0]
000
001
010
pll_clk
fro_hf
main_clk
111
“none”
MCLK
DIVIDER
MCLK pin
(output)
MCLKDIV
MCLK clock select
MCLKCLKSEL[2:0]
000
001
010
fro_hf
fro_12
pll_clk
011
mclk_in
100
main_clk
101
wdt_clk
32k_clk
DMIC CLOCK
DIVIDER
to DMIC
subsystem
to CLK32K of all
Flexcomm Interfaces
(1 per device)
DMICCLKDIV
DMIC clock select
DMICCLKSEL[2:0]
(1 per Flexcomm Interface)
111
“none”
(up to 8 Flexcomm
interfaces on
these devices)
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