LPC5411x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved.
Product data sheet Rev. 2.1 — 9 May 2018 49 of 105
NXP Semiconductors
LPC5411x
32-bit ARM Cortex-M4/M0+ microcontroller
10.2 CoreMark data
[1] Clock source FRO. PLL disabled.
[2] Characterized through bench measurements using typical samples.
[3] Compiler settings: Keil µVision v.5.17., optimization level 3, optimized for time ON.
[4] See the FLASHCFG register in the LPC5411x User Manual for system clock flash access time settings.
[5] Flash is powered down
[6] SRAM1 and SRAM2 powered down. SRAM0 and SRAMX powered.
Table 13. CoreMark score
T
amb
=25
C, V
DD
= 3.3V
Parameter Conditions Typ Unit
ARM Cortex-M4 in active mode; ARM Cortex-M0+ in sleep mode
CoreMark score CoreMark code executed from SRAMX;
CCLK = 12 MHz
[1][2][3][5][6]
2.6 (Iterations/s) / MHz
CCLK = 48 MHz
[1][2][3][5][6]
2.6 (Iterations/s) / MHz
CCLK = 96 MHz
[1][2][3][5][6]
2.6 (Iterations/s) / MHz
CoreMark score CoreMark code executed from flash;
CCLK = 12 MHz; 1 system clock flash
access time.
[1][2][3][4][6]
2.6 (Iterations/s) / MHz
CCLK = 48 MHz; 3 system clock flash
access time.
[1][2][3][4][6]
2.4 (Iterations/s) / MHz
CCLK = 96 MHz; 6 system clock flash
access time.
[1][2][3][4][6]
2.1 (Iterations/s) / MHz
ARM Cortex-M0+ in active mode; ARM Cortex-M4 in sleep mode
CoreMark score CoreMark code executed from SRAMX;
CCLK = 12 MHz
[1][2][3][5][6]
2.0 (Iterations/s) / MHz
CCLK = 48 MHz
[1][2][3][5][6]
2.0 (Iterations/s) / MHz
CCLK = 96 MHz
[1][2][3][5][6]
2.0 (Iterations/s) / MHz
CoreMark score CoreMark code executed from flash;
CCLK = 12 MHz; 1 system clock flash
access time.
[1][2][3][4][6]
2.0 (Iterations/s) / MHz
CCLK = 48 MHz; 3 system clock flash
access time.
[1][2][3][4][6]
1.9 (Iterations/s) / MHz
CCLK = 96 MHz; 6 system clock flash
access time.
[1][2][3][4][6]
1.7 (Iterations/s) / MHz
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