NXP Semiconductors PN544 C2 - Page 89

NXP Semiconductors
UM191812
PN544 C2 User Manual
191812 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
User Manual Rev. 1.2 — 2010-06-16 89 of 172
HOST
PN544
NXP_PL_RDPHASES
Status Phase byte = 0x87
(Type A, B & Felica detection + Pause)
Polling
Loop
Gate
Polling
Loop
Gate
Pause
Reader Phase
Detection
Type A
Pause Phase = 200ms
Type A
Reader
Gate
Type A
Reader
Gate
EVT_READER_REQUESTED
Polling
Loop
Gate
Polling
Loop
Gate
NXP_PL_PAUSE
Pause Phase Duration = 0x1046 = 200 ms
Detection
Type B
Detection
Type F
(1)
Fig 52. Several Reader Phases
Note: it is assumed that the RF Gate initialization has been performed. It means that to
launch the Polling Loop, the EVT_READER_REQUESTED & NXP_PL_RDPHASES are
only needed to start the reader’s phases.
Reader phase(s) and emulation phase
PN544 goes through all the reader phases, then, it goes to emulation phase, during
NXP_PL_EMULATION time. Then it starts again the reader phases, and so on (until a
card or an external reader is detected). The EMULATION phase power mode is the one
set according to PWR_STATUS EEPROM Area value.
(1)
Fig 53. Reader Phases and Emulation Phase