Index
208
floppy disk interface unit. See peripheral devices
G
GPC. See peripheral devices
graphic programming console. See peripheral devices
greater than flag. See data areas
H
HDM(61). See instruction set
high speed counter − HDM(61). See instruction set
high speed drum counter reset. See data areas
high speed timer − TIMH(15). See instruction set
holding relay area. See data areas
HR area. See data areas
I
I/O bits available
in CPUs, 17
in expansion I/O units, 18 , 19
I/O response time, 102
I/O units. See units
IL(02). See instruction set
ILC(03). See instruction set
input bit, definition of, 3
input devices, definition of, 3
input point, definition of, 3
input signal, definition of, 3
instruction set
ADD(30), 90
analog timer unit, 61
AND, 48
combining with OR, 33
use in ladder diagrams, 32
AND LD, 49
combining with OR LD, 109
use in logic blocks, 34 , 108
AND NOT, 48
use in ladder diagrams, 32
BCD(24), 85
BIN(23), 84
CLC(41), 93
CMP(20), 82
CNT, 64
changing set value, 151
CNTR(12), 67
DIFD(14)
as a bit control instruction, 50
use in interlocks, 53
DIFU(13)
as a bit control instruction, 50
use in interlocks, 53
DMPX(77), 87
END(01), 42 , 56 , 121
HDM(61), 68
IL(02), 53
converting to mnemonic code, 120
use in branching, 37
ILC(03), 53
converting to mnemonic code, 120
use in branching, 37
JME(05), 55
JMP(04), 55
KEEP(11)
as a bit control instruction, 51
controlling bit status, 41
LD, 48
use in ladder diagrams, 32
LD NOT, 48
use in ladder diagrams, 32
MLPX(76), 85
MOV(21), 81
MVN(22), 82
NOP(00), 56
NOT, 31
OR, 48
combining with AND, 33
use in ladder diagrams, 33
OR LD, 49
combining with AND LD, 109
use in logic blocks, 34 , 108
OR NOT, 48
use in ladder diagrams, 33
OUT, 49
using to control bit status, 40
OUT NOT, 49
using to control bit status, 40
SFT(10), 77 , 78 , 80
STC(40), 93
SUB(31), 92
TIM, 57
changing set value, 151
TIMH(15), 61
interlock − IL(02). See instruction set
interlock clear − ILC(03). See instruction set
internal relay area. See data areas
inverse condition. See instruction set
IR area. See data areas
J
JME(05). See instruction set
JMP(04). See instruction set
jump − JMP(04). See instruction set
jump end − JME(05). See instruction set
K
KEEP(11). See instruction set
L
ladder diagram
branching
use of, 34
using IL(02) and ILC(03), 37
using JMP(04) and JME(05), 39
using TR bits, 35
converting to mnemonic code, 106