53
HR 000
0500
0002
0003
0004
0005
KEEP
HR 000
Reset input
S
R
Indicates
emergency
situation
Activates
warning
display
KEEP(11) can also be combined with TIM to produce delays in turning bits
ON and OFF. Refer to
5–11–1 Timer – TIM
for details.
5–7 Interlock and Interlock Clear – IL(02) and ILC(03)
Ladder Symbol
IL(02)
Ladder Symbol
ILC(03)
Description
IL(02) is always used in conjunction with ILC(03) to create interlocks. Inter-
locks are used to enable branching in the same way as can be achieved with
TR bits, but treatment of instructions between IL(02) and ILC(03) differs from
that with TR bits when the execution condition for IL(02) is OFF. If the execu-
tion condition of IL(02) is ON, the program will be executed as written, with
an ON execution condition used to start each instruction line from the point
where IL(02) is located through ILC(03). Refer to
4–3–4 Branching Instruc-
tion Lines
for basic descriptions of both methods.
If the execution condition for IL(02) condition is OFF, the interlocked section
between IL(02) and ILC(03) will be treated as shown in the following table:
Instruction Treatment
OUT and OUT NOT Designated bit turned OFF.
TIM and TIMH(15) Reset.
CNT, CNTR(12) PV maintained.
KEEP(11) Bit status maintained.
DIFU(13) and DIFD(14) Not executed (see below).
All others Not executed.
IL(02) and ILC(03) do not necessarily have to be used in pairs. IL(02) can be
used several times in a row, with each IL(02) creating an interlocked section
through the next ILC(03). ILC(03) cannot be used unless there is at least one
IL(02) between it and any previous ILC(03).
Changes in the execution condition for a DIFU(13) or DIFD(14) are not re-
corded if the DIFU(13) or DIFD(14) is in an interlocked section and the exe-
DIFU(13) and DIFD(14) in
Interlocks
Interlock and Interlock Clear Section 5–7
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