Omron SYSMAC CS1 User Manual

6-4SectionAR Area
80
Address Forced
set/reset
Controlled
by
DetailsFunctionBits
AR 09
00
High-speed
counter 1
commands
High-speed
Counter
Start Bit
OFF: Stops counter operation. The
high-speed counter PV is held.
ON: Starts counter operation. The
high-speed counter PV is not reset.
User Enabled
01 High-speed
Counter
Reset Bit
OFF: If the counter reset method is set to a
software reset in the Unit Setup Area
(DM 6605 and DM 6607), the high-speed
counter PV is not cleared when internal I/O
refresh is performed in the Customizable
Counter Unit. If the counter reset method is
set to a phase Z + software reset, phase-Z
input is disabled.
ON: If the counter reset method is set to a
software reset in the Unit Setup Area
(DM 6605 and DM 6607), the high-speed
counter PV is cleared when internal I/O
refresh is performed in the Customizable
Counter Unit. If the counter reset method is
set to a phase Z + software reset, phase-Z
input is enabled.
02 Measure-
ment Start
Bit (mea-
surement
mode 1 or 2)
OFF: Measurement for high-speed counter
rate of change or frequency measurement
is disabled.
ON: Starts measurement for high-speed
counter rate of change or frequency
measurement.
Note 1: Frequency measurement is
possible only with counter 1.
Note 2: This bit is valid only when the
measurement mode set in the Unit Setup
Area (DM 6606 and DM 6608) is set to
high-speed counter rate of change
(measurement mode 1) or frequency
measurement (measurement mode 2).
03 Measure-
ment Direc-
tion Specifi-
cation Bit
(measure-
ment mode
2)
Specifies the direction (up or down) of the
pulse input for which frequency
measurement is performed.
OFF: Up
ON: Down
Note: Be sure to set this bit before turning
ON the Measurement Start Bit.
04 Range
Comparison
Result Clear
Bit
OFF: The instruction execution result
(AR 10) or the output bit pattern (AR 11)
that is output when the CTBL instruction is
executed for a range comparison on the
high-speed counter is not cleared.
ON: The instruction execution result
(AR 10) or the output bit pattern (AR 11)
that is output when the CTBL instruction is
executed for a range comparison on the
high-speed counter is cleared.
05 to
07
(Reserved
by
system.)
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Omron SYSMAC CS1 Specifications

General

Brand	Omron
Model	SYSMAC CS1
Category	Controller
Language	English