Panasonic TH-65PF9UK - DN-Board (2 of 3) Block Diagram

14.19. DN-Board (2 of 3) Block Diagram
P3V_SDA2 P3V_SCL2
P3V_SDA2
P3V_SCL2
P3V_SDA3
P3V_SCL3
P3V_SCL2
P3V_SDA2
+1.5V +2.5V +3.3V
+2.5V
STB+3.3V+3.3V
STB+3.3V+3.3V
+3.3V
+3.3V
+3.3V
+3.3V
+1.5V +3.3V
+3.3V
GO0-9
HDO,VDO,CLKO
BO0-9
RO0-9
BE0-9
GE0-9
RE0-9
HDE,VDE,CLKE-57
RVIA0-9
BUIA0-9
GYIA0-9
DHA,DVA,
DCKA
RVIB0-9
BUIB0-9
GYIB0-9
DHB,DVB,
DCKB
[EVEN]
[ODD]
RV,GY,BU
IC4501
LSI57Plus
RGB OUT
GOUT0-9
BOUT0-9
HP,VP,OCKO
ROUT0-9
DDR-SDRAM I/F
DQ0-DQ31
ADRS0-ADRS11
IC4502
VDD
32M DDR SDRAM
NRST
SCKREF MCKREF
REFCK
OCKREF
I2CSDA
I2CSCL
57_R0-9
57_B0-9
57_G0-9
57_HD,57_VD,57_CLK
IIC_SDA
IIC_SCL
FPGA2
IC5201
LSI57_RIN0-9
LSI57_BIN0-9
LSI57_GIN0-9
LSI57 INPUT
LSI57-HP,-VP,-CLK
IIC_BUS
NRST
REFCK_39.5MHz
OCK-90MHz
FPGA1 INPUT
FPGA_GINE0-9
FPGA_HDE,VDE,CLKE
FPGA_BINE0-9
FPGA_RINE0-9
FPGA_BINO0-9
FPGA_RINO0-9
FPGA_GINO0-9
FPGA_HDO,VDO,CLKO
FPGA_FLD
CLK2X_E
FLD
CLK2X_E
CONFIGURATION
FPGA_NCONFIG
FPGA_DCLK
FPGA_DCLK
FPGA_DATA0
FPGA_NSTATUS
FPGA_CONFDONE
[EVEN]
[ODD]
BUFFER
IC4906
VCC
DIR
IC4907
VCC
DIR
BUFFER
BUFFER
IC4903
VCC
VCC
IC4905
OE1
OE1
BUFFER
BUFFER
VCC
IC4908
OE1
D0,D5-D7,D12-D15
D1-D4,D8-D11
A8-A15
A0-A2,A16,A19,CE2,OE
A3-A7,A17,A18WE
D1-D15
A0-A18
WE,CE,OE
CONFIG-OE
ADDR0-18
NWE,NCE,NOE
FLASH
DATA0-15
DEV-OE
FLASH
GCLK2
IC4302
CPLD(FPGA ROM)
FPGA_NCONFIG
FPGA_DCLK
FPGA_DCLK
FPGA_DATA0
FPGA_NSTATUS
FPGA_CONFDONE
NRST
TDO
TDI
TMS
TCK
8M FLASH MEMORY
IC4902
RESET
VCCDQ1-DQ15
WE,CE,OE
A0-A18
2
RESET
1
VOUTVDD
IC4904
FPGA-TDI
FACTORY USE
2
GND
3
FPGA-TCK
41
FPGA-TMS
DN
10
FOR
FPGA-TDO
5
(FPGA ROM WRITER)
XIN
1
5
LCLK1
SDAT
7
SCLK
IIC_BUS
6
CLOCK BUFFER
IC5103
8
LCLK2
CBCLK_A
X2CBCLK_A
1
X2CBCLK_B
5
XIN
7
SCLK
6
LCLK2
8
CLOCK BUFFER
IC5103
CBCLK_B
LCLK1
SDAT
IIC_BUS
CPG
IC5701
VDD
8
CLK2
(40MHz)
X5701
XT
1
XTN
20
(4.25MHz)
CLK7
8
7
CLK1
(2088MHz)
(74.25MHz)
9
CLK3
(39.5MHz)
12
CLK6
(72MHz)
13
CLK5
OCK_90MHz
14
CLK4
(90MHz)
OSD_72MHz
REFCK39.5MHz
CLK7425-1
CLKM_20MHz
CLK7425
OSD_CLKO
OSD_CLKI
RESET
IIC_CLK
IIC_SDA
IIC_SCL
IIC_BUS
CLKM_20MHz
NRST-FP
OSD_72MHz
PO_CLK
VCC VCC
I-CHIPS PORT1 OUTPUT
PORT1_GOUT0-9
PORT1_BOUT0-9
PORT1_HS,_VS,_CLK
PORT1_ROUT0-9
PORT1_FLD,_ACT
PORT2_BOUTE0-9
PORT2_ROUTE0-9
PORT2_GOUTE0-9
I-CHIPS PORT2 OUTPUT
PORT2_GOUTO0-9
PORT2_BOUTO0-9
PORT2_ROUTO0-9
[EVEN]
[ODD]
PORT2_FLD,_ACT
PORT2_HS,_VS,_CLK
P1_Y/G0-9
P1_PR/R0-9
P1_PB/B0-9
P1_HS,_VS,_CLK
P1_FLD,_ACT
P2_Y/GO0-9
P2_HS,_VS,_CLK
P2_PB/BO0-9
P2_PR/RO0-9
P2_FLD,_ACT
P2_PB/BE0-9
P2_Y/GE0-9
P2_PR/RE0-9
RGB IN PORT1
PI1DO_0-PI1D_29
PI1HSB,PI1VSB,
PI1CLK
PI1FLD,PI1ACTB
PI2DO_0-PI2D_29
PI2FLD,PI2ACTB
PI2HSB,PI2VSB,
PI2CLK
RGB IN PORT2
(60bit)
(30bit)
I-CHIPS
IC5501
INTERFACE
SD-RAM
SD-RAM1 DATA
ADDRESS
POD_0-POD_59
FPGA3 OUTPUT
SD RAM2 DATA
POHSB,POVSB
POFLD,POAVTB
SO
SI
SCLKB
RSTB
POCLK
MCLK
CLK INPUT
CPU I/F
SD_RAM1
WE,CAS,RAS
ADDR0-11
DQ1-DQ31 VCC
IC5502
VCC
WE,CAS,RAS
ADDR0-11
DQ1-DQ31
SD_RAM2
IC5503
MCDATA-0
ICHIPS-SI
MCCLK
ICHIPS-RST
(30bit)
(30bit)
(30bit)
PO_HS,_VS
PO_RO0-9,PO_GO0-9,PO_BO0-9
PO_FLD,_ACT
PO_RE0-9,PO_GE0-9,PO_BE0-9
(60bit)
DN
DIGITAL SIGNAL PROCESSOR/MICOM
10
11
9
4
6
7
1
5
3
8
2
26
24
23
22
21
25
27
TH-65PF9UK
DN-Board (2 of 3) Block Diagram
TH-65PF9UK
DN-Board (2 of 3) Block Diagram
TH-65PF9UK
97