Panasonic TH-65PF9UK - DN-Board (3 of 3) Block Diagram

14.20. DN-Board (3 of 3) Block Diagram
P3V_SDA2
P3V_SCL2
P3V_SDA2 P3V_SCL2
Q4718
STB+1.5V
Q4717
STB+5V
P+15V
STB+3.3V
P5V_DC2 P5V_DC
P5V_DC1
+3.3V
+3.3V
+1.2V
+1.8V
+3.3V+2.5V+1.2V
STB+5V
G2
OUT2
-INC
5
STB 1.5V
S2
FB
CTL
Q4301
VIN
IC4303
VDD
23
21
VDD
21
9
OUT1
VDD
24
DC-DC CONVERTER
CTL
24
VOUT
G2
1
VO
19
G2
VDD
16
17
18
CB
5
P+15V
Q4302
P+15V
DC-DC CONVERTER
FB
OUT2
15V->3.3V
VOUT
19
1
VIN
VIN
CB
IC4307
S1
18
20
15V->1.5V
24
IC4308
IC4304
LX
9
VOUT
D1
IC4301
D1
S2
15V->2.5V
S1
-INC
P_ON/OFF
20
OUT2
OUT1
D2
13
VCC
VO
16
FB
G1
LX
S2
D2
13
-INC
9
LX
S1
+1.5V
23
IC4305
D1
VCC
STB 3.3V
16
Q4303
19
+3.3V
VIN
DC-DC CONVERTER
5
5
4
5
G1
CTL
D2
D1
AVR 5V
5
CB
D2
18
P+15V
17
AVR 5V
VCC
23
VDD
D2
IC4309
D2
G1
20
D1
VOUT
21
VO
17
1
VDD
13
5
OUT1
D1
20
OUT2
VO
17
5
19
D2D2
G1
D1
21
Q4306
CTL
VIN
D1
VDD
CB
-INC
OUT1
18
P+15V
FB
DC-DC CONVERTER
G2
13
IC4306
15V->1.8V
24
LX
S1
+1.8V
9
23
VCC
S2
16
31
61
29
LVDS
11
12
33
44
54
TC-
TA+
DATA
29
TD-
46
23
31
17
25
57
TC+
30
55
TCLK+
21
21
30
TE+
8
TTL
28
TC4
20
10Bit LVDS
48
TCLK-
42
13
TE-
PARALLEL
9
TD+
18
38
50
63
TB-
LVD S
TRANSMITTER
(10bit)
CLKIN
25
4
23
6
TA-
26
24
40
19
(SERIAL)
52
22
24
1
TB+
62
5
TO D5
IC5801
18
DN
51
28
/PDWN
TC5
20
64
59
15
25
4
E-LVDS2
E-LVDSCLK
23
6
TA-
10
7
40
19
E+LVDS3
(SERIAL)
52
E+LVDS2
22
24
1
E-LVDS3
33
TB+
E+LVDS1
9
44
57
E+LVDSCLK
TC+
54
E-LVDS0
TC-
30
TA+
55
DATA
TCLK+
12
21
TD-
5
46
14
29
6
TE+
LVDS
31
8
11
1
TTL
12
11
TC4
4
10Bit LVDS
62
5
18
28
/PDWN
TC5
48
20
TCLK-
E-LVDS1
E+LVDS4
64
42
59
13
TE-
PARALLEL
9
TD+
2
38
50
63
E+LVDS0
E-LVDS4
TB-
CLKIN
61
IC5802
LVD S
TRANSMITTER
(10bit)
VOUT
IC4004
1.2V REG
VIN
8
1
FHQYIN0-9
IIC_BUS
GC5 PROCESOR
IC4001
PORT-FHQ
(GC3E & HQ1)
PORT-E
RGB 30bit OUT
NRST
GOE0-9
BOE0-9
HSOE
VSOE
CLKOE
ROE0-9
FHQCIN0-9
FHQHIN
FHQVIN
FHQCKIN
VCOIN
DN
DIGITAL SIGNAL PROCESSOR/MICOM
+2.5V
[EVEN]
[ODD]
O+LVDSCLK
O-LVDSCLK
O-LVDS1
O+LVDS4
O-LVDS4
O-LVDS3
O+LVDS1
O+LVDS0
O-LVDS0
O-LVDS2
O+LVDS3
O+LVDS2
CONFIGURATION
FPGA_NCONFIG
FPGA_DCLK
FPGA_DCLK
FPGA_DATA0
FPGA_NSTATUS
FPGA_CONFDONE
OSD IN
OSD_HDO
OSD_VDO
OSD_YS
OSD_YM
OSD_CLK
OSD-HD
OSD_DATA0-15
GC_YC OUT
GC_YO0-9
GC_CO0-9
GC_VD
GC_HD
GC_CLK
GC_RGB IN
GC_GIN0-9
GC_RIN0-9
GC_BIN0-9
GC_CLKIN
GC_HSIN
GC_VSIN
PO_VS PO_HS
PO_ACT PO_FLD
PO_RE0-9
[ODD] [EVEN]
PO_GE0-9 PO_BE0-9
PO_GO0-9 PO_BO0-9 PO_RO0-9
I-CHIPS RGB IN
IC5301
FPGA3
CLK1 CLK0
PO_CLK
CLK3 NRST
SDA SCL
CLK_O
VSYNC
ROUT
BOUT
GOUT
HSYNC
LVDS OUT[ODD]
LVDS OUT[EVEN]
HSYNC
GOUT
BOUT
ROUT
VSYNC
CLK_O
+1.5V +2.5V +3.3V
IIC_BUS
CLKM_20MHz
CLK7425-1
CLK7425
NRST-FP
LVDS-PD
26
21
22
25
23
24
27
TH-65PF9UK
DN-Board (3 of 3) Block Diagram
TH-65PF9UK
DN-Board (3 of 3) Block Diagram
TH-65PF9UK
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