Renesas R8C series User Manual

R8C/1A Group, R8C/1B Group 13. Watchdog Timer
Rev.1.30 Dec 08, 2006 Page 105 of 315
REJ09B0252-0130
Figure 13.3 Registers WDTR, WDTS, and CSPR
Watchdog Timer Reset Register
Symbol Address After Reset
WDTR
000Dh Undefined
RW
NOTES :
1.
2.
b0
Do not generate an interrupt betw een w hen 00h and FFh are w ritten.
When the CSPRO bit in the CSPR register is set to 1 (count source protection mode enabled),
0FFFh is set in the w atchdog timer.
WO
b7
Function
When 00h is w ritten before w riting FFh, the w atchdog timer is reset.
(1)
The default value of the w atchdog timer is 7FFFh w hen count source protection
mode is disabled and 0FFFh w hen count source protection mode is enabled.
(2)
Watchdog Timer Start Register
Symbol Address After Reset
WDTS
000Eh Undefined
RW
WO
Function
The w atchdog timer starts counting after a w rite instruction to this register.
b0b7
Count Source Protection Mode Register
Symbol Address After Reset
(1)
CSPR
001Ch 00h
Bit Symbol Bit Name Function RW
NOTES :
1.
2.
—
(b6-b0)
RW
00
Write 0 before w riting 1 to set the CSPRO bit to 1.
0 cannot be set by a program.
When 0 is w itten to the CSPROINI bit in the OFS register, the value after reset is 10000000b.
0
Reserved bits Set to 0.
b3 b2 b1 b0b7 b6 b5 b4
RW
0000
CSPRO
Count source protection mode
select bit
(2)
0 : Count source protection mode disabled
1 : Count source protection mode enabled

Renesas R8C series Specifications

General

Brand	Renesas
Model	R8C series
Category	Computer Hardware
Language	English