Renesas R8C series

R8C/1A Group, R8C/1B Group 14. Timers
Rev.1.30 Dec 08, 2006 Page 127 of 315
REJ09B0252-0130
Figure 14.15 TCSS Register
Timer Count Source Setting Register
Symbol Address After Reset
TCSS
008Eh 00h
Bit Symbol Bit Name Function RW
NOTE :
1.
Reserved bits Set to 0.
0
b1 b0
0 0 : f1
0 1 : f8
1 0 : fRING
1 1 : f2
TXCK0
0
TXCK1
TZCK0
b2 b1 b0
RW
—
(b3-b2)
Reserved bits Set to 0.
RW
b7 b6 b5 b4
00
b3
—
(b7-b6)
Timer X count source select bits
(1)
Do not sw itch count sources during a count operation. Stop the timer count before sw itching count sources.
RW
Timer Z count source select bits
(1)
b5 b4
0 0 : f1
0 1 : f8
1 0 : Selects Timer X underflow .
1 1 : f2
RW
RW
TZCK1
RW