R8C/1A Group, R8C/1B Group 16. Clock Synchronous Serial Interface
Rev.1.30 Dec 08, 2006 Page 171 of 315
REJ09B0252-0130
Figure 16.1 Block Diagram of Clock Synchronous Serial I/O with Chip Select
SSMR register
Data bus
Transmit/receive
control circuit
SSCRL register
SSCRH register
SSER register
SSSR register
SSMR2 register
SSTDR register
SSTRSR register
SSRDR register
Selector
Multiplexer
SSO
SSI
SCS
SSCK
Interrupt requests
(TXI, TEI, RXI, OEI, and CEI)
Internal clock
generation
circuit
f1
Internal clock (f1/i)
i = 4, 8, 16, 32, 64, 128, or 256