Renesas R8C series User Manual

R8C/1A Group, R8C/1B Group 16. Clock Synchronous Serial Interface
Rev.1.30 Dec 08, 2006 Page 217 of 315
REJ09B0252-0130
16.3.3.4 Slave Transmit Operation
In slave transmit mode, the slave device outputs the transmit data while the master device outputs the receive
clock and returns an acknowledge signal.
Figures 16.37 and 16.38 show the Operating Timing in Slave Transmit Mode (I
2
C bus Interface Mode).
The transmit procedure and operation in slave transmit mode are as follows.
(1) Set the ICE bit in the ICCR1 register to 1 (transfer operation enabled). Set bits WAIT and MLS in the
ICMR register and bits CKS0 to CKS3 in the ICCR1 register (initial setting). Set bits TRS and MST in
the ICCR1 register to 0 and wait until the slave address matches in slave receive mode.
(2) When the slave address matches at the 1st frame after detecting the start condition, the slave device
outputs the level set by the ACKBT bit in the ICIER register to the SDA pin at the rise of the 9th clock
cycle. At this time, if the 8th bit of data (R/W
) is 1, bits TRS and TDRE in the ICSR register are set to 1,
and the mode is switched to slave transmit mode automatically. Continuous transmission is enabled by
writing transmit data to the ICDRT register every time the TDRE bit is set to 1.
(3) When the TDRE bit in the ICDRT register is set to 1 after writing the last transmit data to the ICDRT
register, wait until the TEND bit in the ICSR register is set to 1 while the TDRE bit is set to 1. When the
TEND bit is set to 1, set the TEND bit to 0.
(4) The SCL signal is released by setting the TRS bit to 0 and performing a dummy read of the ICDRR
register to end the process.
(5) Set the TDRE bit to 0.

Renesas R8C series Specifications

General

Brand	Renesas
Model	R8C series
Category	Computer Hardware
Language	English

Summary

Notice

Overview of R8C/1A and R8C/1B Groups

Applications

Lists various application areas for electric household appliances, office equipment, and industrial uses.

Performance Overview

Outlines the functions and specifications for R8C/1A and R8C/1B groups.

Notes Regarding These Materials

General Precautions in the Handling of MPU/MCU Products

Handling of Unused Pins

Guidance on handling unused pins to prevent noise induction and potential malfunctions in LSI operation.

Processing at Power-on

Explains the indeterminate states of internal circuits and pins during power supply until reset completion.

Prohibition of Access to Reserved Addresses

States that accessing reserved addresses is prohibited to maintain LSI operation integrity and future expansion.

Clock Signals

Provides instructions on stabilizing clock signals after reset and during program execution.

Differences between Products

Highlights that type numbers within the same group may have differing internal memory and layout patterns.

How to Use This Manual

Purpose and Target Readers

Defines the manual's purpose and the intended audience for understanding hardware functions and electrical characteristics.

Notation of Numbers and Symbols

Register, Bit, and Pin Names Notation

Explains how register, bit, and pin names are referred to using symbols in the text.

Number Notation Conventions

Details the use of 'b' for binary and 'h' for hexadecimal, with no suffix for decimal numbers.

Register Notation Conventions

List of Abbreviations and Acronyms

Special Function Registers (SFRs)

Programmable I/O Ports

Functions of Programmable I/O Ports

Explains how PDi_j bits control I/O ports and the structure of Pi registers, including latch and pin state reading.

Effect on Peripheral Functions

Describes how programmable I/O ports function for peripheral operations, referencing pin name information.

Pins Other Than Programmable I/O Ports

Illustrates the configuration of specific I/O pins that are not programmable, such as RESET and MODE.

Resets

Processor Mode

Bus

Clock Generation Circuit

Notes on Clock Generation Circuit

Covers stop mode, wait mode, oscillation stop detection, and selecting oscillation constants.

Protection

Interrupts

Interrupt Overview

Provides an overview of interrupt types, maskable vs. non-maskable interrupts, and priority.

INT Interrupt

Details the INT0 and INT1 interrupts, including input filters, polarity selection, and registers.

Key Input Interrupt

Explains the key input interrupt generation by pins K10-K13, its use as a wake-up function, and related registers.

Address Match Interrupt

Describes the address match interrupt for debugging, its generation, and associated registers.

Peripheral Function Interrupt

Explains peripheral function interrupts as maskable interrupts generated by internal MCU functions.

Interrupt Control

Details enabling/disabling maskable interrupts and setting priorities using I flag, IPL, and ILVL bits.

Watchdog Timer

Count Source Protection Mode Disabled

Describes watchdog timer specifications when count source protection mode is disabled, using CPU clock.

Count Source Protection Mode Enabled

Details watchdog timer specifications when count source protection mode is enabled, using low-speed oscillator.

Timers

Timer X

Details Timer X, an 8-bit timer with prescaler, covering its modes and associated registers.

Timer Z

Describes Timer Z, an 8-bit timer with prescaler, covering its modes and associated registers.

Timer C

Explains Timer C, a 16-bit timer with input capture and output compare modes, and its registers.

Serial Interface

Clock Synchronous Serial I/O Mode

Explains the clock synchronous serial I/O mode, its configurations, and associated registers.

Clock Asynchronous Serial I/O (UART) Mode

Describes the UART mode for asynchronous serial data transmission and reception, including bit rate settings.

Notes on Serial Interface

Provides important notes on reading and writing serial interface registers, error detection, and data handling.

Clock Synchronous Serial Interface

Mode Selection for Clock Synchronous Serial Interface

Outlines the four modes of the clock synchronous serial interface, including SSU, I2C, communication, and serial modes.

Clock Synchronous Serial I/O with Chip Select (SSU)

Details SSU specifications, including transfer data format, operating modes, master/slave devices, and pins.

I2C Bus Interface

Explains the I2C bus interface specifications, block diagram, timing examples, and associated registers.

A/D Converter

One-Shot Mode for A/D Converter

Details the one-shot mode where a single pin's analog voltage is converted once.

Repeat Mode for A/D Converter

Explains the repeat mode for continuous A/D conversion of a selected pin.

Sample and Hold Function for A/D Converter

Discusses the sample and hold function and its impact on conversion rate and accuracy.

A/D Conversion Cycles

Lists the timing requirements for A/D conversion in various modes and resolutions.

Internal Equivalent Circuit of Analog Input Block

Illustrates the internal equivalent circuit of the analog input block, useful for circuit design.

Inflow Current Bypass Circuit

Explains the configuration and application of inflow current bypass circuits for noise reduction.

Output Impedance of Sensor under A/D Conversion

Addresses the impact of sensor output impedance on A/D conversion accuracy and charging time.

Notes on A/D Converter

Provides essential notes on register access, voltage settings, operating modes, and prohibited instructions.

Flash Memory

Flash Memory Overview

Introduces flash memory rewrite operations in CPU, serial, and parallel I/O modes.

Flash Memory Map

Details the flash memory block diagrams for R8C/1A and R8C/1B groups, showing ROM and data flash areas.

Functions to Prevent Flash Memory Rewriting

Explains ID code check and ROM code protect functions to safeguard flash memory from unauthorized access.

CPU Rewrite Mode for Flash Memory

Describes rewriting the user ROM area directly from the CPU using software commands.

Electrical Characteristics

Absolute Maximum Ratings

Lists critical limits for voltage, power dissipation, and temperature to prevent device damage.

Recommended Operating Conditions

Specifies voltage, clock frequency, and temperature ranges for ensuring reliable device operation.

Usage Notes

Notes on Clock Generation Circuit

Covers precautions for stop mode, wait mode, oscillation stop detection, and selecting oscillation constants.

Notes on Interrupts

Provides notes on reading address 00000h, SP setting, external/key input interrupts, and watchdog timer.

Precautions on Timers

Details precautions for Timer X and Timer Z to ensure correct operation and prevent issues like incorrect counting.

Notes on Serial Interface

Provides notes on serial interface register access, error handling, and data transfer for UART and synchronous modes.

Precautions on Clock Synchronous Serial Interface

Covers precautions for accessing registers and selecting signal pins in clock synchronous serial I/O modes.

Notes on A/D Converter

Provides notes on register operations, voltage settings, operating modes, and prohibited instructions for the A/D converter.

Notes on Flash Memory

Details important notes regarding CPU rewrite mode, operating speed, prohibited instructions, and interrupt handling for flash memory.

Notes on On-Chip Debugger

Package Dimensions

Connection Examples for Serial Writer and On-Chip Debugging Emulator

Example of Oscillation Evaluation Circuit