R8C/1A Group, R8C/1B Group 16. Clock Synchronous Serial Interface
Rev.1.30 Dec 08, 2006 Page 216 of 315
REJ09B0252-0130
Figure 16.36 Operating Timing in Master Receive Mode (I
2
C bus Interface Mode) (2)
SDA
(master output)
SCL
(master output)
12
8967453
b7
b6
b5
b4
b3
b2
b1
b0
SDA
(slave output)
1
0
RCVD bit in
ICCR1 register
1
0
ICDRR register
ICDRS register
Data n-1
Processing
by program
(6) Stop condition
generation
A/A
(8) Set to slave receive mode
9
A
Data n
RDRF bit in
ICSR register
Data n
Data n-1
(5) Set RCVD bit to 1 before
reading ICDRR register
(7) Read ICDRR register before
setting RCVD bit to 0
To Next Page
Loading...
Need help?
General
