Renesas RH850/F1K Series User Manual

RH850/F1K Series Hardware Design Guide
R01AN2911EJ0100 Rev. 1.00 Page 39 of 46
Aug 04, 2016
6.1.3 Combined Debug and Flash Programming Interface Connection of RH850/F1K
Group
The following figure describes the combined connections for debugging and flash programming of the RH850/F1K
group, supporting
 1pin Low-pin debug interface (1pin LPD)
 4pin Low-pin debug interface (4pin LPD)
 Nexus interface
 Single-wire asynchronous flash programming interface with PG-FP5 or E1/RFP
 Two-wire asynchronous flash programming interface with PG-FP5 or E1/RFP
 Synchronous flash programming interface with PG-FP5
Figure 20 RH850/F1K Combined debug and flash programming interface connections
Notes:
1.
The use of an external resistor is only required when the Nexus IF mode is used for debugging
and depends on the hardware specification and implementation of the 3
rd
party development tool.
2.
When the Nexus interface is used for debugging the value of the resistor depends on the 3
rd
party
development tool specification.
3.
The resistor is optional when the 4pin low-pin debug mode is used
4.
The maximum sink current of the RESET terminal of the E1 emulator is 2mA. The external pull-
up circuit of the RESET pin has to be considered based on the applications requirement. When an
external RESET component is used, the pull-up resistor value has to be selected appropriately.
TVDD
GND
GND
GND
VDDVDD
EVCC
EVSS
FPDR/TDI/LPDIO/TxD/SO
FPDT/TDO/LPDO/SI
TCK/LPDCLK/SCK
TMS
TRST/CLK
RDY/LPDCLKOUT
FPMD0
FPMD1
RESET RESET
P10_8 (FLMD1)
FLMD0
JP0_0 (DCUTDI/LPDIO, LPDI)
JP0_1 (DCUTDO/LPDO)
JP0_2 (DCUTCK/LPDCLK)
JP0_3 (DCUTMS)
JP0_4 (DCUTRST)
JP0_5 (DCURDY/LPDCLKOUT)
VDD
1k to 4.7kΩ
Note 3
RH850/F1K Group
E1 Emulator
/
PG-FP5 Flash Programmer
(14pin Connector)
100kΩ
1k to 10kΩ
RDY/LPDCLKOUT
EVTO
JP0_6 (EVTO)
VDD
Note 1
10k to 100kΩ
Note 2
VDD
min. 4.7kΩ
Note 4

Renesas RH850/F1K Series Specifications

General

Brand	Renesas
Model	RH850/F1K Series
Category	Power Supply
Language	English