RH850/F1K Series Hardware Design Guide
R01AN2911EJ0100 Rev. 1.00 Page 19 of 46
Aug 04, 2016
4.2 General Purpose I/O
4.2.1 RESET State of General Purpose I/O
During RESET state, all general-purpose I/O pins are in input mode with high-Z behavior except the pin
P8_6/_RESETOUT.
4.2.2 JP0_4/_DCUTRST
During power-on, RESET the pin JP0_4 should not be driven externally to high-level. Therefore, JP0_4/_DCUTRST
has to be connected in all device operation modes to EVSS via a resistor.
4.2.3 P8_6/_RESETOUT/NMI/CSIH0CSS4/PWGA38O/RTCAOUT/ADCA0I8S
When the _RESETOUT signal is selected for the P8_6 pin the output on the pin is at low level during a reset and after
release from the reset state depending on the option byte setting (OPBT0[9] register).
P8_6 with alternate function
When P8_6 shall be used with an alternate function (e.g. NMI/CSIH0CSS4/PWGA38O/RTCAOUT, etc.), it has to be
considered that the pin P8_6 is on low level after a Power-on RESET or any other device RESET source until it is
released by the application software.
P8_6 and RESETOUT function
The pin P8_6 has an emulated RESETOUT function as default function. By this function, this pin can drive an output to
low-level during and after reset, e.g. to reset an external ASIC. In addition, that RESETOUT function can be disabled
that the pin P8_6 behaves like other pins with high-z during RESET state.
For further details, please refer to the chapter “P8_6: RESETOUT” of the RH850/F1K hardware user’s manual.
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