Renesas RH850/F1K Series - A;D-Converter; Conversion Time; External Multiplexer Wait Time; Figure 12 ADC Conversion Time

RH850/F1K Series Hardware Design Guide
R01AN2911EJ0100 Rev. 1.00 Page 27 of 46
Aug 04, 2016
5. A/D-Converter
5.1 Conversion Time
The ADC conversion time consists of a number of timing parameters, which are summed-up to get the conversion
timing depending on the application.
Figure 12 ADC conversion time
Notes:
1.
SG
- Scan Group
2.
MPX
- External multiplexer
3.
HWTRG
- Hardware trigger
4.
SWTRG
- Software trigger
The setting of the ADC clock and the sampling time results in the following conversion timing:
Table 15 ADC conversion time overview
ADCLK
[MHz]
Sampling
time
[clks]
MPX Setup
time
[µs]
Sampling
time
[µs]
Conversion
time
[µs]
Total
conversion
time
(excluding
MPX)
[µs]
Total
conversion
time
(including
MPX)
[µs]
40
24
1.15
0.60
0.55
1.15
2.30
32
18
1.25
0.56
0.69
1.25
2.50
32
24
1.44
0.75
0.69
1.44
2.88
24
18
1.67
0.75
0.92
1.67
3.33
24
24
1.92
1.00
0.92
1.92
3.83
8
18
5.00
2.25
2.75
5.00
10.00
8
24
5.75
3.00
2.75
5.75
11.50
Note: The sampling time is set by the ADCAnSMPCR.SMPT [7:0] bits.
5.2 External Multiplexer Wait Time
When an external multiplexer is used to extend the number of analogue input channels, a fixed wait time/set-up time of
one conversion time has to be taken into account.
SG setup MPX setup Sampling Conversion SG end
Total conversion time (single channel)
4clks HWTRG
6clks SWTRG
Sampling clock + conversion clocks 18clks or 24clks 4clks22clks