Renesas RH850/F1K Series - Website and Support

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RH850/F1K Series Hardware Design Guide

R01AN2911EJ0100 Rev. 1.00 Page 46 of 46

Aug 04, 2016

Website and Support

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Table of Contents2
Power Supply6
Power Supply Overview of RH850/F1K Group6
Power Supply Pin Overview of RH850/F1K Group6
Power Supply Pin Configuration of RH850/F1K Group6
Power Supply Pin Architecture of RH850/F1K Group6
Table 1 Power Supply Pin Overview6
Figure 1 RH850/F1K Power Supply Architecture7
Table 2 Power Supply Architecture RH850/F1K with Single Supply 5V7
Table 3 Power Supply Architecture RH850/F1K with Single Supply 3.3V7
Table 4 Power Supply Architecture RH850/F1K with Mixed Supply 5V & 3.3V8
Table 5 Power Supply Architecture RH850/F1K with Mixed Supply 5V & 3.3V8
Table 6 Power Supply Architecture RH850/F1K with Mixed Supply 5V & 3.3V9
Table 7 Power Supply Architecture RH850/F1K with Mixed Supply 5V & 3.3V9
Power Supply Timing of RH850/F1K Group10
Figure 2 RH850/F1K Power Up/Down Timing10
Principle Capacitor Placement at REGVCC of RH850/F1K Group11
Figure 3 Principle Capacitor Placement at REGVCC for EMI at Data Flash Operation11
Minimum External Components12
Minimum External Components of RH850/F1K Group12
Figure 4 Minimum External Components for RH850/F1K (176Pin) for Normal Operation Mode12
Table 8 Minimum External Components for RH850/F1K (176Pin)13
Oscillator15
Recommended Oscillator Circuit15
Main Oscillator15
Figure 5 Recommended Main Oscillator Circuit15
Table 9 Guidance Values of the Main Oscillator Circuit15
Sub Oscillator16
Recommended Oscillator Layout16
Figure 6 Recommended Sub Oscillator Circuit16
Table 10 Guidance Values of the Sub Oscillator Circuit16
Device Pins17
Reset17
Minimum RESET Circuit17
Figure 7 Minimum RESET Circuit17
Table 11 Guidance Values for the Minimum RESET Circuit17
RESET Input Characteristics18
Figure 8 External RESET Timing18
General Purpose I/O19
RESET State of General Purpose I/O19
Jp0_4/_Dcutrst19
P8_6/_Resetout/Nmi/Csih0Css4/Pwga38O/Rtcaout/Adca0I8S19
Figure 9 RESETOUT Pin Behavior at OPBT0[9] = 120
Figure 10 RESETOUT Pin Behavior at OPBT0[9] = 020
Analog Filter Function21
Figure 11 Analog Filter Function21
Behavior During Low Power Mode22
Table 12 Behavior During Low Power Mode22
Recommended Connection of Unused Pins23
Recommended Connection of Unused Pins for RH850/F1K Group23
Table 13 Recommended Connection of Unused Pins for RH850/F1K Group23
Pin Assignment Differences25
Table 14 Basic Pin Assignment Differences25
Injected Current26
A/D-Converter27
Conversion Time27
External Multiplexer Wait Time27
Figure 12 ADC Conversion Time27
Table 15 ADC Conversion Time Overview27
Equivalent Input Circuit28
Figure 13 ADC Equivalent Input Circuit28
Table 16 Equivalent Input Circuit of ADCA028
Table 17 Equivalent Input Circuit of ADCA128
External Circuit on ADC Input29
Figure 14 ADC External Circuit on Analog Input29
Table 18 Basic External ADC Input Circuit29
Development and Test Tool Interface31
Table 19 Operation Mode Overview31
Table 20 Operation Mode Description31
Development Tool Interface of RH850/F1K Group32
Debug Interface Connection of RH850/F1K Group32
Figure 15 RH850/F1K 1Pin Low-Pin Debug Interface Connection32
Figure 16 RH850/F1K 4Pin Low-Pin Debug Interface Connection33
Figure 17 RH850/F1K Nexus, 4Pin LPD and 1Pin LPD Debug Interface Connection34
Table 21 Debug Interface Signal Connection of RH850/F1K35
Flash Programming Interface Connection of RH850/F1K Group36
Table 22 Basic Flash Programming Connection of RH850/F1K36
Figure 18 RH850/F1K PG-FP5 Flash Programming Interface Connection37
Table 23 PG-FP5 Flash Programming Signal Connection of RH850/F1K37
Figure 19 RH850/F1K E1 Flash Programming Interface Connection38
Table 24 E1 Flash Programming Signal Connection of RH850/F1K38
Combined Debug and Flash Programming Interface Connection of RH850/F1K Group39
Figure 20 RH850/F1K Combined Debug and Flash Programming Interface Connections39
Debug and Flash Programming Interface Connection of RH850/F1K Group When the Internal HSOSC Is Used as Clock Supply40
Figure 21 RH850/F1K Debug and Flash Programming Interface Connections When the HSOSC Is Used as Clock Supply40
Debug Considerations When Hot Plug-In Is Used42
Figure 22 Circuit Configuration for Hot Plug-In42
Boundary Scan Mode Interface of RH850/F1K Group43
Figure 23 Boundary Scan Connection of RH850/F1K43
Reference Documents44
Abbreviations45
Website and Support46
Revision History47
General Precautions in the Handling of MPU/MCU Products48

Renesas RH850/F1K Series - Website and Support

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