Schweitzer Engineering Laboratories SEL-321 - Page 23

Date Code 20011026 Specifications iii
SEL-321/321-1 Instruction Manual
Table 2.17: Remote Bit Summary (SEL-321-1 Relay Only).................................................................. 2-33
Table 2.18: Intermediate Elements (SEL-321-1 Relay Only).................................................................2-33
Table 2.19: Intermediate Element Summary (SEL-321-1 Relay Only)..................................................2-33
Table 2.20: Internal Elements (SEL-321-1 Relay Only) ........................................................................2-34
Table 2.21: Internal Element Summary (SEL-321-1 Relay Only) .........................................................2-34
Table 2.22: Input/Output Contact Targets (One I/O Board Version, SEL-321-1 Relay Only).............2-36
Table 2.23: Input/Output Contact Targets (Two I/O Board Version, SEL-321-1 Relay Only) ............2-37
Table 2.24: Input/Output Contact Targets Summary (One I/O Board Version and Two I/O Board
Version, SEL-321-1 Relay Only).................................................................................2-37
Table 2.25: Setting Group Selections .....................................................................................................2-39
Table 2.26: Fault Location Triggering Elements....................................................................................2-41
Table 2.27: INST and TIME LED Qualifying Elements........................................................................2-42
Table 2.28: Communications Ports Specifications.................................................................................2-44
Table 2.29: Self-Test Summary ..............................................................................................................2-46
FIGURES
Figure 2.1: Signal Connections Between Relay and Communication Equipment................................2-12
Figure 2.2: SEL-321 SELOGIC Control Equations Overview...............................................................2-21
Figure 2.3: SEL-321 Front-Panel Targeting .........................................................................................2-41
Figure 2.4: Logic Symbol Legend.........................................................................................................2-54
Figure 2.5: Zone 1 Mho Phase Distance Element Logic ......................................................................2-55
Figure 2.6: Zone 2 Mho Phase Distance Element Logic ......................................................................2-55
Figure 2.7: Zone 3 Mho Phase Distance Element Logic ......................................................................2-56
Figure 2.8: Zone 4 Mho Phase Distance Element Logic ......................................................................2-56
Figure 2.9: Supervisory Phase-to-Phase Overcurrent Elements ...........................................................2-57
Figure 2.10: Zone 1 Mho Ground Distance Element Logic....................................................................2-57
Figure 2.11: Zone 2 Mho Ground Distance Element Logic....................................................................2-58
Figure 2.12: Zone 3 Mho Ground Distance Element Logic....................................................................2-58
Figure 2.13: Zone 4 Mho Ground Distance Element Logic....................................................................2-58
Figure 2.14: Zone 1 Quadrilateral Ground Distance Element Logic......................................................2-59
Figure 2.15: Zone 2 Quadrilateral Ground Distance Element Logic......................................................2-59
Figure 2.16: Zone 3 Quadrilateral Ground Distance Element Logic......................................................2-59
Figure 2.17: Zone 4 Quadrilateral Ground Distance Element Logic......................................................2-59
Figure 2.18: Supervisory Phase Overcurrent Elements ..........................................................................2-60
Figure 2.19: Out-of-Step Distance Element Logic..................................................................................2-61
Figure 2.20: Out-of-Step Block and Trip Logic......................................................................................2-62
Figure 2.21: Load-Encroachment Logic .................................................................................................2-63
Figure 2.22: Negative-Sequence Directional Element Logic..................................................................2-64
Figure 2.23: Phase Time-Overcurrent Element Logic (SEL-321 Relay Base Version) .........................2-65
Figure 2.24: Phase Time-Overcurrent Element Logic (SEL-321-1 Relay Only)....................................2-65
Figure 2.25: Negative-Sequence Time-Overcurrent Element Logic.......................................................2-66
Figure 2.26: Residual Time-Overcurrent Element Logic........................................................................2-67
Figure 2.27: Negative-Sequence Overcurrent Element Logic for Levels 1 - 4.......................................2-68
Figure 2.28: Residual Overcurrent Element Logic for Levels 1 - 4........................................................2-69
Figure 2.29: Voltage Element Logic.......................................................................................................2-70
Figure 2.30: Positive-Sequence Overvoltage Element Logic .................................................................2-71
Figure 2.31: Permissive Overreaching Transfer Trip Scheme Logic ..................................................... 2-71
Figure 2.32: Directional Comparison Unblocking Scheme Logic.......................................................... 2-72