Schweitzer Engineering Laboratories SEL-321 - Page 24

iv Specifications Date Code 20011026
SEL-321/321-1 Instruction Manual
Figure 2.33: Directional Comparison Blocking Scheme Logic - 1 of 2 .................................................2-72
Figure 2.34: Directional Comparison Blocking Scheme Logic - 2 of 2 .................................................2-72
Figure 2.35: Zone 1 Extension Logic......................................................................................................2-73
Figure 2.36: Remote-End-Just-Opened Logic.........................................................................................2-73
Figure 2.37: Switch-Onto-Fault Enable Logic........................................................................................2-73
Figure 2.38: Loss-of-Potential Logic ......................................................................................................2-74
Figure 2.39: Pole-Discordance and Trip During Pole Open Logic......................................................... 2-75
Figure 2.40: Pole Open Logic .................................................................................................................2-76
Figure 2.41: Stub Protection Logic .........................................................................................................2-76
Figure 2.42: Trip Coil Monitor Logic.....................................................................................................2-76
Figure 2.43: Close Logic.........................................................................................................................2-77
Figure 2.44: Trip Suspicion Logic ..........................................................................................................2-77
Figure 2.45: Open Phase Alarm Logic.................................................................................................... 2-77
Figure 2.46: Trip Decision Logic for Phase A........................................................................................2-78
Figure 2.47: Trip Latch Logic.................................................................................................................2-78
Figure 2.48: Trip Unlatch Logic for Phase A .........................................................................................2-79
Figure 2.49: Ground and Phase Distance Speed Curves.........................................................................2-80
Figure 2.50: Time Curve U1 ...................................................................................................................2-83
Figure 2.51: Time Curve U2 ...................................................................................................................2-83
Figure 2.52: Time Curve U3 ...................................................................................................................2-83
Figure 2.53: Time Curve U4 ...................................................................................................................2-83
Figure 2.54: Time Curve C1 ...................................................................................................................2-84
Figure 2.55: Time Curve C2 ...................................................................................................................2-84
Figure 2.56: Time Curve C3 ...................................................................................................................2-84
Figure 2.57: Time Curve C4 ...................................................................................................................2-84