Fail-Safe signal module (SM) I/O configuration
5.4 Configuring SM 1226 F-DQ 4 x 24 VDC DQ and channel parameters
S7-1200 Functional Safety Manual
Manual, 02/2015, A5E03470344-AA
111
Configuring SM 1226 F-DQ 4 x 24 VDC DQ and channel
parameters
Table 5- 4 SM 1226 F-DQ 4 x 24 VDC DQ parameters
Maximum test period Assign the time interval between bit pattern
tests for F-DQ DC output faults.
Functional test bit patterns are applied to the
output switches. These tests detect faulted P-
or M- output switches and wiring faults that
are detectable at the module terminals. Short
circuits to other signals or power rails can be
detected. Open circuits between the wiring
terminals and the load are not detected.
If an error is detected on a channel, the test
interval is shortened to approx. 1 min. If an
error is no longer detected, the configured
test interval is used again.
A persistent fault is reported to the fail-safe
CPU and the affected channels are passivat-
1000 s
• 100 s
• 1000 s