Technical specifications
A.3 Fail-Safe signal module (SM) technical specifications
S7-1200 Functional Safety Manual
Manual, 02/2015, A5E03470344-AA
181
Switching of loads
Connecting capacitive loads
Load capacitance can delay the voltage response as seen at the P- and M- switches of the
SM 1226 F-DQ 4 x 24 VDC. For a capacitive load with capacitance C across P and M, and a
parallel load resistance R, the "Maximum readback time" needs to be longer than 1 time
constant (R * C) of the load. This allows enough time for an appreciable voltage change to
be seen when you briefly de-energize an energized load during bit pattern testing. If the
resulting "Maximum readback time" is too long for your application, you can reduce this time
constant by adding parallel resistance across the load to reduce the realized R * C time
constant.
Stray capacitance between the load circuit and ground, M, and P increases the time required
for the "Maximum readback time switch on test". When module diagnostics switch "ON" a P
or M switch to a de-energized load during bit pattern testing, both sides of the load are driven
towards L+ or M, limited by stray capacitance. This effect is typically small.
Your "Maximum readback time switch on test" should be long enough for the load circuit
voltage to react, but short enough that if one side of the load faults to P or M, testing of the
opposite switch should not cause the load to mechanically react.
Capacitive loads (including power supplies with input capacitors) with low series resistance
can have a large inrush current. If you have a large capacitive load, you should add series
resistance to reduce the inrush current to reduce the risk of opened fuses or overcurrent fault
detection on normal load switch ON events.
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