2 Functions
182
7SA522 Manual
C53000-G1176-C155-3
If the unblock frequency is received from the opposite end, a signal is routed to the trip
logic. A pre-condition for fast fault clearance is therefore that the earth fault is recog-
nized in the forward direction at both line ends.
The send signal can be prolonged by T
S
(settable). The prolongation of the send signal
only comes into effect if the protection has already issued a trip command. This
ensures that the permissive signal releases the opposite line end even if the earth fault
is very rapidly cleared by a different independent protection.
Figure 2-79 Operation scheme of the directional unblocking scheme
Sequence Figure 2-80 shows the logic diagram of the unblocking scheme for one line end.
The directional unblocking scheme only functions for faults in the “forward” direction.
Accordingly the overcurrent stage intended for operation in the directional unblocking
scheme must definitely be set to )RUZDUG (,',5(&7,21); refer also to Sub-
section 2.7 at the margin heading “Teleprotection with Earth Fault Protection”.
On two terminal lines, the signal transmission may be phase segregated. Send and
receive circuits in this case are built up for each phase. On three terminal lines, the
transmit signal is sent to both opposite line ends. The receive signals are then com-
bined with a logical AND gate, as all three line ends must transmit a send signal during
an internal fault. With the setting parameter /LQH&RQILJ (address ) the
device is informed as to whether it has one or two opposite line ends.
An unblock logic is inserted before the receive logic, which in essence corresponds to
that of the directional comparison scheme, see Figure 2-81. If an interference free
unblock signal is received, a receive signal e.g. ´!()8%XEµ, appears and the
blocking signal e.g. ´!()8%EOµ disappears. The internal signal “Unblock 1” is
forwarded to the receive logic where it initiates the release of the tripping (when all re-
maining conditions have been fulfilled).
If the transmitted signal does not reach the other line end because the short circuit on
the protected feeder causes too much attenuation or reflection of the transmitted
signal, the unblock logic takes effect: Neither the unblocking signal ´!()8%XEµ
nor the monitoring signal ´!()8%EOµ are received. In this case, the release “Un-
block 1” is issued after a security delay time of 20 ms and passed onto the receive
logic. This release is however removed after a further 100 ms via the timer stage
100/100 ms. If the interference signal disappears again, one of the two receive signals
must appear again, either ´!()8%XEµ or ´!()8%EOµ; after a further 100
ms (dropout delay of the timer stage 100/100 ms) the quiescent state is reached again
i.e. the direct release path to the signal “Unblock L1” and thereby the usual release is
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