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Spirent SmartBits System
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Chapter 9: Ethernet Cards
Gigabit Ethernet Testing, Clock Tolerance
134 SmartBits System Reference
Know How the Test Works
With multiple ports under tests, it is important to understand exactly what the test is doing
to understand the different results that can occur.
As an example, the Smart Applications Back-to-Back test is not a full mesh test, and it
works in port pairs. If you ran a 24-port test and got certain results, then moved the cables
around, you could get very different results. This test stops when any one of the port pairs
sees an error (loss of packets), and reruns the test for a shorter amount of time. If this
passes, it runs the test for a longer length of time using a binary algorithm. If the DUT uses
a single master transmit clock for all of the transmitting output ports, you can move the
cables around and your results should not change unless the DUT treats its ports with
different priorities. However, if the ports use different clock sources, some ports may be
slower that others, and there will be differences in the results.
Know How the Test Equipment Works
Understanding the test analysis equipment also impacts results. The SMB-2000 uses a
GX-1405 SmartCard for each test port. Each of these cards has its own crystal oscillator
(with 50ppm tolerance), so there can be different tolerances for each port. The SMB-
6000B uses LAN-3200A modules that have two printed circuit board (PCB) cards on each
module with two ports on each PCB. There is one crystal oscillator (with 25ppm
tolerance) for each PCB (pair of ports).
Know How the DUT Works
How the DUT assigns its buffer space to the ports can affect test results. If the total data
buffer space is dynamically assigned so that ports that need more of the buffer pool can
access that space, this helps to average out the port differences for a longer period of time
before data loss. If the total buffer space is statically assigned per port, tests similar to the
Back-to-Back test would fail the device faster if there are large clock tolerances
differences from port to port.

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