12.4 Octo‑SPI flash memory
The MX25UM51245GXDI00 Macronix OctaFlash
™
memory has the following characteristics: 512 Mbit, 1v8,
200 MHz, DTR. It is managed through the Octo‑SPI interface.
The MB1829 main board supports at least an 80 MHz DTR setting. To reach these performances, the HSLV
feature of MCU is activated for the Octo‑SPI interface.
The NRST reset pin from the microcontroller manages the Octo‑SPI flash RESET function.
The embedded footprint is also compatible with many other references in the BGA24 package, check the
compatibility of the memory datasheet versus MB1829 schematics.
Table 13. Octo‑SPI flash I/O interface
PIO Configuration
PA2 NCS (OCTOSPIM_P1.NCS)
PA1 DQS (OCTOSPIM_P1.DQS)
PF10 CLK (OCTOSPIM_P1.CLK)
PF8 IO0 (OCTOSPIM_P1.IO0)
PF9 IO1 (OCTOSPIM_P1.IO1)
PF7 IO2 (OCTOSPIM_P1.IO2)
PF6 IO3 (OCTOSPIM_P1.IO3)
PC1 IO4 (OCTOSPIM_P1.IO4)
PC2 IO5 (OCTOSPIM_P1.IO5)
PC3 IO6 (OCTOSPIM_P1.IO6)
PC0 IO7 (OCTOSPIM_P1.IO7)
NRST NRESET (NRESET)
12.5 eMMC flash memory
The MTFC4GACAJCN-1M WT Micron eMMC flash memory has the following characteristics: 4‑GByte, eMMC
V5.0, HS200/HS400, and DDR up to 52 MHz.
The MB1829 main board supports at least the following modes: DDR mode at 40 MHz (no HSLV PIO mode) or
SDR mode at 80 MHz in HS200 mode (with HSLV PIO mode).
The eMMC_RSTn (PH6, active low) is the reset for eMMC.
UM2967
Octo‑SPI flash memory
UM2967 - Rev 1
page 32/68
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