Sun Microsystems Ultra 45 User Manual

11-6 Sun Ultra 45 and Ultra 25 Workstations Service and Diagnostics Manual • May 2006
reset reason: 0000.0000.0000.0001
Fire TLU-A OE Error status: 0003.0100.0000.0100
@(#)OBP 4.21.x 2005/09/28 16:12 Sun Ultra 45
Clearing TLBs
Executing Power On Self Test
Q0>
OpenBoot PROM prepares to run
POST
.
0>@(#) Sun Ultra 45 POST 4.21.x 2005/11/05 19:58
POST build version and date is
displayed.
/dat/fw/common-source/firmware_re/post/post-build-
4.21.0/Ultra/Ultra45/integrated (firmware_re)
POST build path is displayed.
0>Copyright © 2005 Sun Microsystems, Inc. All rights
reserved
SUN PROPRIETARY/CONFIDENTIAL.
Use is subject to license terms.
Copyright and license are
displayed.
0>Soft Power-on RST thru SW
0>OBP->POST Call with %o0=00001000.01014000.
0>Diag level set to MAX.
0>Verbosity level set to MAX.
0>MFG scrpt mode set NORM
0>I/O port set to TTYA.
CPU0 is acknowledged and POST
configuration is read from
register.
0>Start Selftest.....
0>CPUs present in system: 0
0>Test CPU(s).....
0>Initialize I2C Controller
0>Init CPU
0>DMMU
0>DMMU TLB DATA RAM Access
0>DMMU TLB TAGS Access
0>IMMU Registers Access
0>IMMU TLB DATA RAM Access
0>IMMU TLB TAGS Access
0>Init mmu regs
CPU, I
2
C controller, data memory
management unit (DMMU), and
instruction memory management
unit (IMMU) are initialized.
0>Setup L2 Cache
0>L2 Cache Control = 00000000.00f04400
0> Size = 00000000.00100000...
0>L2 Cache Tags Test
0>Scrub and Setup L2 Cache
L2 cache is set up and scrubbed
(data values set to defaults).
0>Setup and Enable DMMU
0>Setup DMMU Miss Handler
DMMU is set up.
0>Test Mailbox
0>Scrub Mailbox
Mailbox region is checked and
initialized in L2 cache.
TABLE 11-6 post max max Output Comparison (Continued)
Output Displayed What Is Happening

Sun Microsystems Ultra 45 Specifications

General

Brand	Sun Microsystems
Model	Ultra 45
Category	Desktop
Language	English