Chapter 11 Power-On Self-Test 11-9
0>Setup Final DMMU Entries
Memory is allocated for POST.
0>Post Image Region Scrub
Allocated memory is scrubbed
clean.
0>Run POST from Memory
POST is transferred from ROM to
RAM memory. POST is executed
from memory from this point
forward.
0>Verifying checksum on copied image.
0>The Memory’s CHECKSUM value is f482.
0>The Memory’s Content Size value is 8c57a.
0>Success... Checksum on Memory Validated.
Copied data is verified.
0>Test CPU Caches.....
CPU internal caches are tested.
0>I-Cache RAM Test
0>I-Cache Tag RAM
0>I-Cache Valid/Predict TAGS Test
0>I-Cache Snoop Tag Field
0>I-Cache Branch Predict Array Test
Instruction cache is tested.
0>Branch Prediction Initialization
0>D-Cache RAM
0>D-Cache Tags
0>D-Cache Micro Tags
0>D-Cache SnoopTags Test
0>W-Cache RAM
0>W-Cache Tags
0>W-Cache Valid bit Test
0>W-Cache Bank valid bit Test
0>W-Cache SnoopTAGS Test
Data and write caches are tested.
0>P-Cache RAM
0>P-Cache Tags
0>P-Cache SnoopTags Test
0>P-Cache Status Data Test
Prefetch cache is tested.
0>8k DMMU TLB 0 Data
0>8k DMMU TLB 1 Data
0>8k DMMU TLB 0 Tags
0>8k DMMU TLB 1 Tags
0>8k IMMU TLB Data
0>8k IMMU TLB Tags
Translation look-aside buffers
(TLB) are tested for data and
instruction buffers.
0>FPU Registers and Data Path
0>FPU Move Registers
Floating point unit (FPU) is
checked.
0>FSR Read/Write
FPU status register is checked.
TABLE 11-6 post max max Output Comparison (Continued)
Output Displayed What Is Happening
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