Theory of Operation-2445A/2455A Service
normal operating limit
and
change the output voltage of
the thermal sensor.
The
amplitude of this
de
level
is
periodically checked via comparator U2510
and
DAC
U2101
(on
diagram
2)
and
allows the Microprocessor to
detect when
an
overload condition
is
present.
When
an
overload occurs, the processor switches the input coupling
to the 1 þÿM©position to prevent damage to the attenuator
and
displays
50
þÿ©
OVERLOAD
on
the crt.
Compensating capacitor
C105
is
adjusted at the time of
calibration to normalize input capacitance of the
preamplifier to the attenuator.
A probe-coding ring around the
BNC
input connector
passes probe coding information
(a
resistance to ground)
to the Analog Control circuitry for detection of probe
attenuation factors.
The
readout scale factors
are
set to
reflect the detected attenuation factor of the attached
probe.
Auxiliary Control Register
The
Auxiliary Control Register allows the Microproces-
sor to control various mode and
range
dependent func-
tions of the instrument. Included
in
these functions
are:
attenuation factors, input coupling, Channel 3
and
Channel
4 gains, vertical-bandwidth limiting,
and
the
X-Y
display
mode.
When
the Microprocessor sets the input coupling mode
and
attenuation factors for Channel 1
and
Channel
2,
a
series of eight, 16-bit control words
are
serially clocked
into shift registers U140
and
U150 (eight bits
in
each
regis-
ter).
Each
control word is
used
to set the position of one
of
the eight attenuator
and
coupling relays (four relays are
in
each
attenuator assembly).
Each
control word will have
only the bit corresponding to the specific relay contact to
be
closed set
HI.
Relay
buffers U110
and
U130A (for
Channel
1)
and
U120
and
U130B (for
Channel
2)
are
Dar-
lington configurations that invert the polarities of
all
bits.
This results
in
a
LO
being applied to only the
coil
lead
associated with the contact to
be
closed;
all
other coil
leads
are
held
HI.
To set a
relay
once the control word
is
loaded, the
Microprocessor generates a ATTN STAB (attenuator
strobe) to U130G
pin
7
via
R129
and
C130. The strobe
pulses the output of U130G
LO
for a short time. This out-
put pulse attempts to turn
on
both 0130
and
0131 (relay
drivers) via their identical base-bias networks.
Due
to the
lower
level
from the turned
on
Darlington relay buffer (cou-
pled
through the associated
coil
diode
and
either CR130 or
CR131
to one of the bias networks), one transistor will
turn
on
harder
as
the ATTN STAB pulse begins to forward
bias the transistors. The more positive collector voltage of
the transistor turning
on
harder is
fed
through the bias
3-14
diode
(again
either
CR
130 or
CR
131) to further turn off the
opposite transistor. This action results
in
one transistor
being fully
on
and
the other one
being
fully off.
The
saturated transistor sources current through the two
stacked
relay
coils to the
LO
output of either U140 or
U150 (current sink) to close the selected contacts.
Once
set, the magnetic-latch feature will hold the relay set to
this position until opposing data
is
clocked into the Aux-
iliary Control Register and strobed into the
relay.
All
coil
leads for the remaining relays are set
HI,
and
only the
selected
relay
will
be
set.
To set the
seven
remaining Attenuator
and
coupling
relays, the sequence just described is repeated
seven
more times. Whenever the Microprocessor determines that
the attenuation factor or input coupling
has
changed, the
entire relay-setting procedure
is
repeated for
all
eight
relays.
After the coupling
and
attenuator relays have
been
latched into position, the Auxiliary Control Register
is
free
to
be
used
for further circuit-eontrolling tasks. Eight more
bits of control data are then clocked into U 140 either to
enable or disable the following functions: vertical
bandwidth limiting
(BWL),
triggered
X-
Y mode
(TXY),
the A
and
B Sweep
Delay
Comparators (BDCA
and
BDCA), and
slow-speed intensity limit (SIL); or to alter the Channel 3
and
Channel
4 gain factors
(GA3
and
GA4)
. Two other
bits are clocked into register U150: one to produce the
CTC
signal
and
the other
to
control the scale illumination
circuit during SGL
SEQ
display mode. The CTC control bit
is
used
to enable a sweep-start linearity circuit
in
the A
Sweep circuitry (diagram
5)
on
the 2
ns
and
20
ns
per divi-
sion sweeps.
Analog Control Demultiplexer
When
enabled
by
the Address Decode circuitry, Analog
Control Demultiplexer U170 directs the analog levels
applied to
pin
3 from
DAC
U2101
(diagram
2)
to one of six
sample-and-hold circuits.
In
the Preamplifier circuitry, the
sample-and-hold circuits maintain the
VAR
gain
and
DC
Bal
control-voltage levels applied to both the Channel 1
and
Channel
2 Preamplifiers U100
and
U200 between
updates. Two of the Demultiplexers outputs direct analog
levels to the Holdoff
and
Channel 2
Delay
offset sample-
and-hold circuits (diagram
5).
Routing
is
determined
by
the
three-bit address from register
U2301
(diagram
2)
applied
to Demultiplexer U170
on
pins
9,
10,
and
11.
Channel 1 Preamplifier
Channel
1 Preamplifier U100 converts the single-ended
input signal from the Channel 1 Attenuator to a differential
output signal
used
to drive the Vertical Channel Switch.
The
device produces either amplification or attenuation
in
predefined increments, depending
on
the control data writ-
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