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DMA Registers
DMA1CFGH (0xD3) – DMA Channel 1–4 Configuration Address High Byte
Bit Name Reset R/W Description
7:0
DMA1CFG[15:8]
0x00 R/W The DMA channel 1–4 configuration address, high-order
DMA1CFGL (0xD2) – DMA Channel 1–4 Configuration Address Low Byte
Bit Name Reset R/W Description
7:0
DMA1CFG[7:0]
0x00 R/W The DMA channel 1–4 configuration address, low-order
DMAIRQ (0xD1) – DMA Interrupt Flag
Bit Name Reset R/W Description
7:5 – 000 R0 Reserved
4
DMAIF4
0 R/W0 DMA channel-4 interrupt flag
0: DMA channel transfer not complete
1: DMA channel transfer complete/interrupt pending
3
DMAIF3
0 R/W0 DMA channel-3 interrupt flag
0: DMA channel transfer not complete
1: DMA channel transfer complete/interrupt pending
2
DMAIF2
0 R/W0 DMA channel-2 interrupt flag
0: DMA channel transfer not complete
1: DMA channel transfer complete/interrupt pending
1
DMAIF1
0 R/W0 DMA channel-1 interrupt flag
0: DMA channel transfer not complete
1: DMA channel transfer complete/interrupt pending
0
DMAIF0
0 R/W0 DMA channel-0 interrupt flag
0: DMA channel transfer not complete
1: DMA channel transfer complete/interrupt pending
105
SWRU191C–April 2009–Revised January 2012 DMA Controller
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