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Timer 1 Registers
T1CCTL2 (0xE7) – Timer 1 Channel 2 Capture/Compare Control
Bit Name Reset R/W Description
7
RFIRQ
0 R/W When set, use RF interrupt for capture instead of regular capture input.
6
IM
1 R/W Channel 2 interrupt mask. Enables interrupt request when set.
5:3
CMP[2:0]
000 R/W Channel 2 compare mode select. Selects action on output when timer value equals compare value in
T1CC2.
000: Set output on compare
001: Clear output on compare
010: Toggle output on compare
011: Set output on compare-up, clear on compare-down in up-down mode. Otherwise set output on
compare, clear on 0.
100: Clear output on compare-up, set on compare-down in up-down mode. Otherwise clear output
on compare, set on 0.
101:
Clear when equal T1CC0, set when equal T1CC2
110:
Set when equal T1CC0, clear when equal T1CC2
111:
Initialize output pin. CMP[2:0] is not changed.
2
MODE
0 R/W Mode. Select Timer 1 channel 2 capture or compare mode
0: Capture mode
1: Compare mode
1:0
CAP[1:0]
00 R/W Channel 2 capture-mode select
00: No capture
01: Capture on rising edge
10: Capture on falling edge
11: Capture on all edges
T1CC2H (0xDF) – Timer 1 Channel 2 Capture/Compare Value, High
Bit Name Reset R/W Description
7:0
T1CC2[15:8]
0x00 R/W Timer 1 channel 2 capture/compare value high-order byte. Writing to this register when
T1CCTL2.MODE = 1 (compare mode) causes the T1CC2[15:0] update to the written value to be
delayed until T1CNT = 0x0000.
T1CC2L (0xDE) – Timer 1 Channel 2 Capture/Compare Value, Low
Bit Name Reset R/W Description
7:0
T1CC2[7:0]
0x00 R/W Timer 1 channel 2 capture/compare value low-order byte. Data written to this register is stored in
a buffer but not written to T1CC2[7:0] until, and at the same time as, a later write to T1CC2H
takes effect.
121
SWRU191C–April 2009–Revised January 2012 Timer 1 (16-Bit Timer)
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