Timer 3 and Timer 4 DMA Triggers
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The SFR register TIMIF contains all interrupt flags for Timer 3 and Timer 4. The register bits
TIMIF.TxOVFIF and TIMIF.TxCHnIF contain the source interrupt flags for the two terminal-count value
events and the four channel-compare events, respectively. A source interrupt flag is set when the
corresponding event occurs, regardless of interrupt mask bits. The CPU interrupt flag IRCON.T3IF or
IRCON.T4IF is set when one of the events occurs if the corresponding interrupt mask bit is equal to 1.
The interrupt mask bits are TxCCTLn.IM for the four channels and TxCTL.OVFIM for the overflow events.
The CPU interrupt flag IRCON.T3IF or IRCON.T4IF is also set when a Timer 3 or Timer 4 source
interrupt flag is being cleared and one or more other source interrupt flags for the same timer are still set
while the corresponding interrupt mask bit is set. An interrupt request is generated when IRCON.TxIF
goes from 0 to 1 if IEN1.TxIEN and IEN0.EA are both equal to 1 (x is 3 or 4).
10.7 Timer 3 and Timer 4 DMA Triggers
Two DMA triggers are associated with Timer 3, and two DMA triggers are associated with Timer 4.
• T3_CH0: Timer 3 channel 0 capture/compare
• T3_CH1: Timer 3 channel 1 capture/compare
• T4_CH0: Timer 4 channel 0 capture/compare
• T4_CH0: Timer 4 channel 1 capture/compare
10.8 Timer 3 and Timer 4 Registers
T3CNT (0xCA) – Timer 3 Counter
Bit Name Reset R/W Description
7:0
CNT[7:0]
0x00 R Timer count byte. Contains the current value of the 8-bit counter
T3CTL (0xCB) – Timer 3 Control
Bit Name Reset R/W Description
7:5
DIV[2:0]
000 R/W Prescaler divider value. Generates the active clock edge used to clock the timer from
CLKCONCMD.TICKSPD as follows:
000: Tick frequency/1
001: Tick frequency/2
010: Tick frequency/4
011: Tick frequency/8
100: Tick frequency16
101: Tick frequency /32
110: Tick frequency/64
111: Tick frequency/128
4
START
0 R/W Start timer. Normal operation when set, suspended when cleared
3
OVFIM
1 R/W Overflow interrupt mask
0: Interrupt is disabled.
1: Interrupt is enabled.
2
CLR
0 R0/W1 Clear counter. Writing a 1 to CLR resets the counter to 0x00 and initializes all output pins of
associated channels. Always read as 0.
1:0
MODE[1:0]
00 R/W Timer 3 mode. Select the mode as follows:
00: Free-running, repeatedly count from 0x00 to 0xFF
01: Down, count from T3CC0 to 0x00
10: Modulo, repeatedly count from 0x00 to T3CC0
11: Up/down, repeatedly count from 0x00 to T3CC0 and down to 0x00
128
Timer 3 and Timer 4 (8-Bit Timers) SWRU191C– April 2009–Revised January 2012
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