RF Core
www.ti.com
23.1 RF Core
The RF Core controls the analog radio modules. In addition, it provides an interface between the MCU
and the radio which makes it possible to issue commands, read status, and automate and sequence radio
events.
The FSM submodule controls the RF transceiver state, the transmitter and receiver FIFOs, and most of
the dynamically controlled analog signals, such as power up/down of analog modules. The FSM is used to
provide the correct sequencing of events (such as performing an FS calibration before enabling the
receiver/transmitter). Also, it provides step-by-step processing of incoming frames from the demodulator:
reading the frame length, counting the number of bytes received, checking the FCS, and finally, optionally
handling automatic transmission of ACK frames after successful frame reception. It performs similar tasks
in TX, including performing an optional CCA before transmission and automatically going to RX after the
end of transmission to receive an ACK frame. Finally, the FSM controls the transfer of data between
modulator/demodulator and the TXFIFO/RXFIFO in RAM.
The modulator transforms raw data into I/Q signals to the transmitter DAC. This is done in compliance
with the IEEE 802.15.4 standard.
The demodulator is responsible for retrieving the over-the-air data from the received signal.
The amplitude information from the demodulator is used by the automatic gain control (AGC). The AGC
adjusts the gain of the analog LNA so that the signal level within the receiver is approximately constant.
The frame filtering and source matching supports the FSM in the RF Core by performing all operations
needed in order to do frame filtering and source address matching, as defined by IEEE 802.15.4.
The frequency synthesizer (FS) generates the carrier wave for the RF signal.
The command strobe processor (CSP) processes all commands issued by the CPU. It also has a short
program memory of 24 bytes, making it possible to automate CSMA-CA algorithms.
The radio RAM holds a FIFO for transmit data (TXFIFO) and a FIFO for receive data (RXFIFO). Both
FIFOs are 128 bytes long. In addition, the RAM holds parameters for frame filtering and source matching,
and for which 128 bytes are reserved.
Timer 2 (MAC Timer) is used for timing of radio events and to capture time stamps of incoming packets.
This timer keeps counting even in power modes PM1 and PM2.
23.1.1 Interrupts
The radio is associated with two interrupt vectors on the CPU. These are the RFERR interrupt (interrupt
0) and the RF interrupt (interrupt 12) with the following functions.
• RFERR: Error situations in the radio are signaled using this interrupt.
• RF: Interrupts coming from normal operation are signaled using this interrupt.
The RF interrupt vector combines the interrupts in RFIF. Note that these RF interrupts are rising-edge
triggered. Thus, an interrupt is generated when, e.g., the SFD status flag goes from 0 to 1. The RFIF
interrupt flags are described in Section 23.1.2.
23.1.2 Interrupt Registers
Two of the main interrupt control SFR registers are used to enable the RF and RFERR interrupts. These
are the following:
• RFERR: IEN0.RFERRIE
• RF: IEN2.RFIE
Two main interrupt flag SFR registers hold the RF and RFERR interrupt flags. These are the following:
• RFERR: TCON.RFERRIF
• RF: S1CON.RFIF
The two interrupts generated by the RF Core are a combination of several sources within the RF Core.
Each of the individual sources has its own enable and interrupt flags in the RF Core. Flags can be found
in RFIRQF0, RFIRQF1, and RFIERRF. Interrupt masks can be found in RFIRQM0, RFIRQM1, and RFERRM.
220
CC253x Radio SWRU191C–April 2009–Revised January 2012
Submit Documentation Feedback
Copyright © 2009–2012, Texas Instruments Incorporated
To Next Page
Loading...
Need help?
General
