Flash Programming
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The third data byte consists of bits 7–0 of the hardware breakpoint. Thus, the second and third data bytes
set the CPU CODE address at which to stop execution.
3.4 Flash Programming
Programming of the on-chip flash is performed via the debug interface. The external host must initially
send instructions using the DEBUG_INSTR debug command to perform the flash programming with the
flash controller.
3.4.1 Lock Bits
For software and/or access protection, a set of lock bits can be written to the upper available flash
page—the lock-bit page. The lock-bit structure consists of FLASH_PAGES-1 lock bits followed by one
debug lock bit (see Table 3-5). The structure starts at address (flash-page size in bytes - 16) in the lock-bit
page and occupies up to 16 bytes. The rest of the lock-bit page (addresses 0–(flash-page size in bytes -
17)) can be used to store code/constants, but cannot be changed without entering debug mode.
The PAGELOCK[FLASH_PAGES-2:0] lock-protect bits are used to enable erase/write protection for
individual flash memory pages (2 KB). There is one bit for each available page.
When the debug-lock bit, DBGLOCK, is set to 0 (see Table 3-5), all debug commands except
CHIP_ERASE, READ_STATUS, and GET_CHIP_ID are disabled. The status of the debug-lock bit can be
read using the READ_STATUS command (see Section 3.3.2).
Note that after the debug-lock bit has changed due to a write to the lock-bit page or a CHIP_ERASE
command, the device must be reset to lock/unlock the debug interface.
Issuing a CHIP_ERASE command is the only way to clear the debug-lock bit, thereby unlocking the debug
interface.
Table 3-5 defines the 16-byte structure containing the flash lock-protection bits. Bit 0 of the first byte
contains the lock bit for page 0, bit 1 of the first byte contains the lock bit for page 1, and so on. Bit 7 of
the last byte in the flash is the DBGLOCK bit (bit 127 in the structure).
Table 3-5. Flash Lock-Protection Bit Structure Definition
Bit Name Description
127
DBGLOCK
Debug-lock bit
0: Disable debug commands
1: Enable debug commands
FLASH_PAGES-2:0
PAGELOCK[FLASH_PAGES-2:0]
Page-lock bits. There is one bit for each of the up to 128 pages.
Page-lock bits for unavailable pages are not used.
0: Page locked
1: Page not locked
3.5 Debug Interface and Power Modes
Power modes PM2 and PM3 may be handled in two different ways when the chip is in debug mode. The
default behavior is never to turn off the digital voltage regulator. This emulates power modes while
maintaining debug mode operation. The clock sources are turned off as in ordinary power modes. The
other option is to turn off the 1.8-V internal digital power. This leads to a complete shutdown of the digital
part, which disables debug mode. When the chip is in debug mode, the two options are controlled by
configuration bit 5 (SOFT_POWER_MODE).
The debug interface still responds to a reduced set of commands while in one of the power modes. The
chip can be woken up from sleep mode by issuing a HALT command to the debug interface. The HALT
command brings the chip up from sleep mode in the halted state. The RESUME command must be issued
to resume software execution.
The debug status may be read when in power modes. The status must be checked when leaving a power
mode by issuing a HALT command. The time needed to power up depends on which power mode the
chip is in, and must be checked in the debug status. The debug interface only accepts commands that are
available in sleep mode before the chip is operational.
60
Debug Interface SWRU191C–April 2009–Revised January 2012
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