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25-6. Address Structure for Basic Mode..................................................................................... 303
25-7. RAM-Based Registers in RAM Page 5................................................................................ 304
25-8. Register Settings for Different CRCs.................................................................................. 307
25-9. Register Settings for Some Commonly Used CRCs, Assuming Initialization With All 1s ...................... 308
25-10. Supported Modulation Formats, Data Rates, and Deviations...................................................... 309
25-11. Segments for Holding ACK Payload for Each Address Entry...................................................... 313
25-12. Commands From MCU to LL Engine via RFST Register .......................................................... 315
25-13. Timer 2 Capture Settings ............................................................................................... 316
25-14. End-of-Task Causes..................................................................................................... 317
25-15. Recommended RAM Register Settings for Start Tone.............................................................. 319
25-16. Interrupt and Counter Operation for Received Messages.......................................................... 320
25-17. Interrupt and Counter Operation for Received Messages.......................................................... 321
25-18. End-of-Receive Tasks................................................................................................... 322
25-19. Interrupt and Counter Operation for Received ACK Packets ...................................................... 325
25-20. End-of-Transmit Tasks .................................................................................................. 326
25-21. Additional Reasons for End-of-Transmit on Clear-Channel Tasks ................................................ 327
25-22. Packet-Sniffer Modes of Operation.................................................................................... 331
25-23. XREG Register Overview............................................................................................... 332
25-24. Registers That Should Be Updated From Their Default Value, Bit Rates 1 Mbps and Lower................. 333
25-25. Registers That Should Be Updated From Their Default Value, Bit Rate 2 Mbps ............................... 333
14
List of Tables SWRU191C–April 2009–Revised January 2012
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