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Registers
DC_I_L (0x61FC) – In-Phase DC Offset Estimate, Low Byte
Bit
Name Reset R/W Description
No.
7:0
DC_I[7:0]
0x00 R*/W When running dc estimation, this register reflects the 8 LSBs of the dc
estimate in the I channel. When manual dc override is selected, the
override value is written to this register.
DC_I_H (0x61FD) – In-Phase DC Offset Estimate, High Byte
Bit
Name Reset R/W Description
No.
7:0
DC_I[15:8]
0x00 R*/W When running dc estimation, this register reflects the 8 MSBs of the dc
estimate in the I channel. When manual dc override is selected, the
override value is written to this register.
DC_Q_L (0x61FE) – Quadrature-Phase DC Offset Estimate Low Byte
Bit
Name Reset R/W Description
No.
7:0
DC_Q[7:0]
0x00 R*/W When running dc estimation. this register reflects the 8 LSBs of the dc
estimate in the Q channel. When manual dc override is selected, the
override value is written to this register.
DC_Q_H (0x61FF) – Quadrature-Phase DC Offset Estimate High Byte
Bit
Name Reset R/W Description
No.
7:0
DC_Q[15:8]
0x00 R*/W When running dc estimation, this register reflects the 8 MSBs of the dc
estimate in the Q channel. When manual dc override is selected, the
override value is written to this register.
IVCTRL (0x6265) – Analog Control Register
Bit
Name Reset R/W Description
No.
7:6 – 00 R0 Reserved
5:4
TX_MIX_LOAD
01 R/W Controls load capacitor in Tx mixer
00: Minimum load
... (Intermediate loads)
11: Maximum load
3
LODIV_BIAS_CTRL
0 R/W Controls bias current to LODIV
0: IVREF bias
1: PTAT bias
2
TXMIX_DC_CTRL
0 R/W Controls dc bias in TXMIX
1:0
PA_BIAS_CTRL
11 R/W Controls bias current to PA
00: IREF bias
01: IREF and IVREF bias
10: PTAT bias
11: Increased PTAT slope bias
353
SWRU191C–April 2009–Revised January 2012 CC2541 Proprietary Mode Radio
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