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Peripheral I/O
• 1: Channel 1 capture/compare pin
P2SEL.PRI1P1 selects the order of precedence when assigning several peripherals to Port 1. The Timer
4 channels have precedence when the bit is set.
7.6.4 USART 0
The SFR register bit PERCFG.U0CFG selects whether to use alternative 1 or alternative 2 locations.
In Table 7-1, the USART 0 signals are shown as follows:
UART:
• RX: RXDATA
• TX: TXDATA
• RT: RTS
• CT: CTS
SPI:
• MI: MISO
• MO: MOSI
• C: SCK
• SS: SSN
P2DIR.PRIP0 selects the order of precedence when assigning several peripherals to Port 0. When set to
00, USART 0 has precedence. Note that if UART mode is selected and hardware flow control is disabled,
USART 1 or Timer 1 has precedence to use ports P0.4 and P0.5.
P2SEL.PRI3P1 and P2SEL.PRI0P1 select the order of precedence when assigning several peripherals
to Port 1. USART 0 has precedence when both are set to 0. Note that if UART mode is selected and
hardware flow control is disabled, Timer 1 or Timer 3 has precedence to use ports P1.2 and P1.3.
7.6.5 USART 1
The SFR register bit PERCFG.U1CFG selects whether to use alternative 1 or alternative 2 locations.
In Table 7-1, the USART 1 signals are shown as follows:
UART:
• RX: RXDATA
• TX: TXDATA
• RT: RTS
• CT: CTS
SPI:
• MI: MISO
• MO: MOSI
• C: SCK
• SS: SSN
P2DIR.PRIP0 selects the order of precedence when assigning several peripherals to Port 0. When set to
01, USART 1 has precedence. Note that if UART mode is selected and hardware flow control is disabled,
USART 0 or Timer 1 has precedence to use ports P0.2 and P0.3.
P2SEL.PRI3P1 and P2SEL.PRI2P1 select the order of precedence when assigning several peripherals
to Port 1. USART 1 has precedence when the former is set to 1 and the latter is set to 0. Note that if
UART mode is selected and hardware flow control is disabled, USART 0 or Timer 3 has precedence to
use ports P1.4 and P1.5.
85
SWRU191C–April 2009–Revised January 2012 I/O Ports
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